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datasheet rl78/g1c renesas mcu integrated usb controller, true low power platform (as low as 112.5 a/mhz, and 0.61 a for rtc + lvd), 2.4 v to 5.5 v operation, 32 kbyte flash, 31 dmips at 24 mhz, for all usb based applications page 1 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 r01ds0348ej0110 rev.1.10 nov 15, 2013 1. outline 1.1 features ultra-low power technology ? 2.4 v to 5.5 v operation from a single supply ? stop (ram retained): 0.23 a, (lvd enabled): 0.31 a ? halt (rtc + lvd): 0.57 a ? supports snooze ? operating: 71 a/mhz 16-bit rl78 cpu core ? delivers 31 dmips at maximum operating frequency of 24 mhz ? instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle ? mac: 16 x 16 to 32-bit result in 2 clock cycles ? 16-bit barrel shifter for shift & rotate in 1 clock cycle ? 1-wire on-chip debug function code flash memory ? density: 32 kb ? block size: 1 kb ? on-chip single voltage flash memory with protection from block erase/writing ? self-programming with secure boot swap function and flash shield window function data flash memory ? data flash with background operation ? data flash size: 2 kb ? erase cycles: 1 million (typ.) ? erase/programming voltage: 2.4 v to 5.5 v ram ? 5.5 kb size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 24 mhz with +/ ? 1% accuracy over voltage (2.4 v to 5.5 v) and temperature ( ? 20c to +85c) ? pre-configured settings: 48 mhz, 24 mhz (typ.) reset and supply management ? power-on reset (por) monitor/generator ? low voltage detection (lvd) with 9 setting options (interrupt and/or reset function) usb ? complying with usb version 2.0, incorporating host/function controller ? corresponding to full-speed transfer (12 mbps) and low-speed (1.5 mbps) ? complying with battery charging specification revision 1.2 ? compliant with the 2.1a/1.0a charging mode prescribed in the apple inc. mfi specification in the usb power supply component specification note direct memory access (dma) controller ? up to 2 fully programmable channels ? transfer unit: 8- or 16-bit multiple communication interfaces ? up to 2 x i 2 c master ? up to 1 x i 2 c multi-master ? up to 2 x csi (7-, 8-bit) ? up to 1 x uart (7-, 8-, 9-bit) extended-function timers ? multi-function 16-bit timer tau: up to 4 channels (remote control output available) ? real-time clock (rtc): 1 channel (full calendar and alarm function with watch correction function) ? 12-bit interval timer: 1 channel ? 15 khz watchdog timer: 1 channel (window function) rich analog ? adc: up to 9 channels, 8/10-bit resolution, 2.1 s minimum conversion time ? internal voltage reference (1.45 v) ? on-chip temperature sensor safety features (iec or ul 60730 compliance) ? flash memory crc calculation ? ram parity error check ? ram write protection ? sfr write protection ? illegal memory access detection ? clock stop/frequency detection ? adc self-test ? i/o port read back function (echo) general purpose i/o ? 5 v tolerant, high-current (up to 20 ma per pin) ? open-drain, internal pull-up support operating ambient temperature ? standard: ? 40c to + 85c ? extended: ? 40c to + 105c package type and pin count ? 32-pin plastic hwqfn (5 x 5) ? 32-pin plastic lqfp (7 x 7) ? 48-pin plastic lfqfp (7 x 7) ? 48-pin plastic hwqfn (7 x 7) note to use the apple inc. battery charging mode, you must join in apple's made for ipod/iphone/ipad (mfi) licensing program. before requesting this specification from renesas electronics, please join in the apple's mfi licensing program.
rl78/g1c 1. outline page 2 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 ? rom, ram capacities flash rom data flash ram rl78/g1c 32-pin 48-pin 32 kb 2 kb 5.5 kb note r5f10jbc, r5f10kbc r5f10jgc, r5f10kgc note this is about 4.5 kb when the self-programming function is used. (for details, see chapter 3 cpu architecture in the rl78/g1c user?s manual: hardware .) remark the functions mounted depend on the product. see 1.6 outline of functions . 1.2 list of part numbers pin count package usb function fields of application note part number 32 pins 32-pin plastic hwqfn (5 5, 0.5 mm pitch) host/function controller a r5f10jbcana#u0, r5f10jbcana#w0 g r5f10jbcgna#u0, r5f10jbcgna#w0 function controller only a r5f10kbcana#u0, r5f10kbcana#w0 g r5f10kbcgna#u0, r5f10kbcgna#w0 32-pin plastic lqfp (7 7, 0.8 mm pitch) host/function controller a r5f10jbcafp#v0, r5f10jbcafp#x0 g r5f10jbcgfp#v0, r5f10jbcgfp#x0 function controller only a r5f10kbcafp#v0, r5f10kbcafp#x0 g r5f10kbcgfp#v0, r5f10kbcgfp#x0 48 pins 48-pin plastic lfqfp (7 7, 0.5 mm pitch) host/function controller a r5f10jgcafb#v0, r5f10jgcafb#x0 g r5f10jgcgfb#v0, r5f10jgcgfb#x0 function controller only a r5f10kgcafb#v0, r5f10kgcafb#x0s g r5f10jgcana#u0, r5f10jgcana#w0 48-pin plastic hwqfn (7 7, 0.5 mm pitch) host/function controller a r5f10jgcana#u0, r5f10jgcana#w0 g r5f10jgcgna#u0, r5f10jgcgna#w0 function controller only a r5f10kgcana#u0, r5f10kgcana#w0 g r5f10kgcgna#u0, r5f10kgcgna#w0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g1c . caution the part number above is valid as of when th is manual was issued. for the latest part number, see the web page of the target product on the renesas electronics website.
rl78/g1c 1. outline page 3 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 figure 1-1. part number, memory size, and package of rl78/g1c part no. r 5 f 1 0 j g c a x x x f b # v 0 packing #u0 : tray (hwqfn) #v0 : tray (lqfp, lfqfp) #w0 : embossed tape (hwqfn) #x0 : embossed tape (lqfp, lfqfp) package rom number (blank product is omitted) rom capacity rl78/g1c group renesas microcontroller renesas semiconductor fp : lqfp, 0.80 mm pitch fb : lfqfp, 0.50 mm pitch na : hwqfn, 0.50 mm pitch c : 32 kb pin count b : 32-pin g : 48-pin 10j : usb host / function controller mounted 10k : usb function controller mounted classification a : consumer use, operating ambient temperature: ? 40 c to +85 c g : industrial use, operating ambient temperature: ? 40 c to +105 c type of memory f : flash data memory
rl78/g1c 1. outline page 4 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 1.3 pin configuration (top view) 1.3.1 32-pin products ? 32-pin plastic hwqfn (5 5 mm, 0.5 mm pitch) (1) usb function: host/function controller (r5f10jbc) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/ani16/to00/intp9/sck01/scl01/(scla0) p00/ani17/ti00/intp8/si01/sda01/(sdaa0) p120/ani19/so01/(pclbuz1) p51/intp2/so00/txd0/tooltxd/(ti01)/(to01) p50/intp1/si00/rxd0/toolrxd/sda00/(ti02)/(to02) p30/intp3/sck00/scl00/(ti03)/(to03)/(pclbuz0) p70/pclbuz1/uovrcur0 p31/ti03/to03/intp4/pclbuz0/uvbusen0 p62 p61/sdaa0 p60/scla0 exposed die pad udp0 udm0 uv bus uv dd udp1 udm1 p16/ti01/to01/intp5/uovrcur1 p17/ti02/to02/uvbusen1 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g1c 1. outline page 5 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) usb function: function controller only (r5f10kbc) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/ani16/to00/intp9/sck01/scl01/(scla0) p00/ani17/ti00/intp8/si01/sda01/(sdaa0) p120/ani19/so01/(pclbuz1) p51/intp2/so00/txd0/tooltxd/(ti01)/(to01) p50/intp1/si00/rxd0/toolrxd/sda00/(ti02)/(to02) p30/intp3/sck00/scl00/(ti03)/(to03)/(pclbuz0) p70/pclbuz1 p31/ti03/to03/intp4/pclbuz0 p62 p61/sdaa0 p60/scla0 exposed die pad udp0 udm0 uv bus uv dd ic note ic note p16/ti01/to01/intp5 p17/ti02/to02 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark note ic: internal connection pin. leave open. caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g1c 1. outline page 6 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 ? 32-pin plastic lqfp (7 7 mm, 0.8 mm pitch) (1) usb function: host/function controller (r5f10jbc) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/ani16/to00/intp9/sck01/scl01/(scla0) p00/ani17/ti00/intp8/si01/sda01/(sdaa0) p120/ani19/so01/(pclbuz1) p51/intp2/so00/txd0/tooltxd/(ti01)/(to01) p50/intp1/si00/rxd0/toolrxd/sda00/(ti02)/(to02) p30/intp3/sck00/scl00/(ti03)/(to03)/(pclbuz0) p70/pclbuz1/uovrcur0 p31/ti03/to03/intp4/pclbuz0/uvbusen0 p62 p61/sdaa0 p60/scla0 udp0 udm0 uv bus uv dd udp1 udm1 p16/ti01/to01/intp5/uovrcur1 p17/ti02/to02/uvbusen1 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware.
rl78/g1c 1. outline page 7 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) usb function: function controller only (r5f10kbc) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/ani16/to00/intp9/sck01/scl01/(scla0) p00/ani17/ti00/intp8/si01/sda01/(sdaa0) p120/ani19/so01/(pclbuz1) p51/intp2/so00/txd0/tooltxd/(ti01)/(to01) p50/intp1/si00/rxd0/toolrxd/sda00/(ti02)/(to02) p30/intp3/sck00/scl00/(ti03)/(to03)/(pclbuz0) p70/pclbuz1 p31/ti03/to03/intp4/pclbuz0 p62 p61/sdaa0 p60/scla0 udp0 udm0 uv bus uv dd ic note ic note p16/ti01/to01/intp5 p17/ti02/to02 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark note ic: internal connection pin leave open. caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware.
rl78/g1c 1. outline page 8 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 1.3.2 48-pin products ? 48-pin plastic lfqfp (7 7, 0.5 mm pitch) (1) usb function: host/function controller (r5f10jgc) 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 udp0 udm0 uv bus uv dd udp1 udm1 p14/uovrcur0 p15/pclbuz1/uvbusen0 p16/ti01/to01/intp5/uovrcur1 p17/ti02/to02/uvbusen1 p51/intp2/so00/txd0/tooltxd p50/intp1/si00/rxd0/toolrxd/sda00 p120/ani19 p41/(ti03)/(to03)/(intp4)/(pclbuz1) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p00/ti00/(sdaa0) p01/to00/(scla0) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scla0 p61/sdaa0 p62 p63 p31/ti03/to03/intp4 p75/kr5/intp9/sck01/scl01 p74/kr4/intp8/si01/sda01 p73/kr3/so01 p72/kr2/(ti02)/(to02) p71/kr1/(ti01)/(to01)/(intp5) p70/kr0 p30/intp3/rtc1hz/sck00/scl00 index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware.
rl78/g1c 1. outline page 9 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) usb function: function controller only (r5f10kgc) 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 udp0 udm0 uv bus uv dd ic note ic note p14 p15/pclbuz1 p16/ti01/to01/intp5 p17/ti02/to02 p51/intp2/so00/txd0/tooltxd p50/intp1/si00/rxd0/toolrxd/sda00 p120/ani19 p41/(ti03)/(to03)/(intp4)/(pclbuz1) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p00/ti00/(sdaa0) p01/to00/(scla0) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scla0 p61/sdaa0 p62 p63 p31/ti03/to03/intp4 p75/kr5/intp9/sck01/scl01 p74/kr4/intp8/si01/sda01 p73/kr3/so01 p72/kr2/(ti02)/(to02) p71/kr1/(ti01)/(to01)/(intp5) p70/kr0 p30/intp3/rtc1hz/sck00/scl00 index mark note ic: internal connection pin leave open. caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware.
rl78/g1c 1. outline page 10 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 ? 48-pin plastic whqfn (7 7, 0.5 mm pitch) (1) usb function: host/function controller (r5f10jgc) 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 udp0 udm0 uv bus uv dd udp1 udm1 p14/uovrcur0 p15/pclbuz1/uvbusen0 p16/ti01/to01/intp5/uovrcur1 p17/ti02/to02/uvbusen1 p51/intp2/so00/txd0/tooltxd p50/intp1/si00/rxd0/toolrxd/sda00 p120/ani19 p41/(ti03)/(to03)/(intp4)/(pclbuz1) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p00/ti00/(sdaa0) p01/to00/(scla0) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scla0 p61/sdaa0 p62 p63 p31/ti03/to03/intp4 p75/kr5/intp9/sck01/scl01 p74/kr4/intp8/si01/sda01 p73/kr3/so01 p72/kr2/(ti02)/(to02) p71/kr1/(ti01)/(to01)/(intp5) p70/kr0 p30/intp3/rtc1hz/sck00/scl00 exposed die pad index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g1c 1. outline page 11 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) usb function: function controller only (r5f10kgc) 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 udp0 udm0 uv bus uv dd ic note ic note p14 p15/pclbuz1 p16/ti01/to01/intp5 p17/ti02/to02 p51/intp2/so00/txd0/tooltxd p50/intp1/si00/rxd0/toolrxd/sda00 p120/ani19 p41/(ti03)/(to03)/(intp4)/(pclbuz1) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p00/ti00/(sdaa0) p01/to00/(scla0) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scla0 p61/sdaa0 p62 p63 p31/ti03/to03/intp4 p75/kr5/intp9/sck01/scl01 p74/kr4/intp8/si01/sda01 p73/kr3/so01 p72/kr2/(ti02)/(to02) p71/kr1/(ti01)/(to01)/(intp5) p70/kr0 p30/intp3/rtc1hz/sck00/scl00 exposed die pad index mark note ic: internal connection pin leave open. caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8. format of peripheral i/o redirection register (pior) in the rl78/g1c user?s manual: hardware. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g1c 1. outline page 12 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 1.4 pin identification ani0 to ani7, ani16, ani 17, ani19: analog input av refm : analog reference voltage minus av refp : analog reference voltage plus exclk: external clock input (main system clock) exclks: external clock input (sub system clock) intp0 to intp6, intp8, intp9: external interrupt input kr0 to kr5: key return p00, p01: port 0 p14 to p17: port 1 p20 to p27: port 2 p30, p31: port 3 p40, p41: port 4 p50, p51: port 5 p60 to p63: port 6 p70 to p75: port 7 p120 to p124: port 12 p130, p137: port 13 p140: port 14 pclbuz0, pclbuz1: programmable clock output/buzzer output regc: regulator capacitance reset: reset rtc1hz: real-time clock correction clock (1 hz) output rxd0: receive data sck00, sck01: serial clock input/output scla0, scl00, scl01: serial clock i nput/output sdaa0, sda00, sda01: serial data input/output si00, si01: serial data input so00, so01: serial data output ti00 to ti03: timer input to00 to to03: timer output tool0: data input/output for tool toolrxd, tooltxd: data input/output for external device txd0: transmit data udm0, udm1, udp0, udp1: usb input/output uovrcur0, uovrcur1: usb input uvbusen0, uvbusen1: usb output uv dd : usb power supply/usb regulator capacitance uv bus : usb input/usb power supply (usb optional bc) v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock) xt1, xt2: crystal oscillator (subsystem clock)
rl78/g1c 1. outline page 13 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 1.5 block diagram 1.5.1 32-pin products port 1 p16, p17 port 2 p20 to p24 5 port 3 p30, p31 2 port 4 port 5 2 port 12 p121, p122 p40 p50, p51 2 voltage regulator regc interrupt control ram window watchdog timer low-speed on-chip oscillator power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator pll on-chip debug tool0/p40 serial array unit0 (2ch) uart0 iic00 rxd0/p50 txd0/p51 timer array unit (4ch) ch2 ti02/to02/p17 ch3 ti03/to03/p31 ch0 ch1 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 a/d converter 5 ani0/p20 to ani4/p24 3 ani16/p01, ani17/p00, ani19/p120 av refp /p20 av refm /p21 2 p120 port 13 p137 scl00/p30 sda00/p50 iic01 ti00/p00 to00/p01 bcd adjustment usb voltage regulator sck00/p30 so00/p51 si00/p50 csi00 v ss toolrxd/p50, tooltxd/p51 v dd uv dd serial interface iica0 sdaa0/p61 scla0/p60 2 intp5/p16 multiplier& divider, mulitiply- accumulator port 0 p00, p01 2 buzzer output pclbuz0/p31, pclbuz1/p70 clock output control csi01 uovrcur0 uvbusen0 usb uovrcur1 uvbusen1 udm0 udp0 udp1 uv bus udm1 direct memory access control port 6 port 7 p70 p60 to p62 3 2 ti01/to01/p16 real-time clock rl78 cpu core code flash memory data flash memory 12-bit interval timer 2 intp8/p00, intp9/p01 scl01/p01 sda01/p00 sck01/p01 so01/p120 si01/p00
rl78/g1c 1. outline page 14 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 1.5.2 48-pin products port 1 p14 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 4 port 12 p121 to p124 p40, p41 2 p50, p51 2 voltage regulator regc interrupt control ram window watchdog timer low-speed on-chip oscillator power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator pll on-chip debug tool0/p40 serial array unit0 (2ch) uart0 iic00 rxd0/p50 txd0/p51 scl00/p30 sda00/p50 timer array unit (4ch) ch2 ti02/to02/p17 ch3 ti03/to03/p31 ch0 ch1 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140 intp1/p50, intp2/p51 a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 4 p120 p140 port 13 p130 p137 ani19/p120 iic01 scl01/p75 sda01/p74 ti00/p00 to00/p01 bcd adjustment usb voltage regulator sck00/p30 so00/p51 si00/p50 csi00 v ss toolrxd/p50, tooltxd/p51 v dd uv dd serial interface iica0 sdaa0/p61 scla0/p60 2 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00, p01 2 buzzer output pclbuz0/p140, pclbuz1/p15 clock output control key return 6 kr0/p70 to kr5/p75 sck01/p75 so01/p73 si01/p74 csi01 uovrcur0 uvbusen0 usb uovrcur1 uvbusen1 udm0 udp0 udp1 uv bus udm1 direct memory access control port 6 port 7 p70 to p75 6 p60 to p63 4 port 14 2 ti01/to01/p16 rtc1hz/p30 real-time clock rl78 cpu core code flash memory data flash memory 12-bit interval timer
rl78/g1c 1. outline page 15 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 1.6 outline of functions [32-pin, 48-pin products] (1/2) item 32-pin 48-pin r5f10jbc r5f10kbc r5f10jgc r5f10kgc code flash memory (kb) 32 kb 32 kb data flash memory (kb) 2 kb 2 kb ram (kb) 5.5 kb note 1 5.5 kb note 1 memory space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscillation, external main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 5.5 v, 1 to16 mhz: v dd = 2.4 to 5.5 v high-speed on-chip oscillator 1 to 24 mhz (v dd = 2.7 to 5.5 v), 1 to 16 mhz (v dd = 2.4 to 5.5 v) pll clock 6, 12, 24 mhz note 2 : v dd = 2.4 to 5.5 v subsystem clock ? xt1 (crystal) oscillation 32.768 khz (typ.): v dd = 2.4 to 5.5 v low-speed on-chip oscillator on-chip oscillation (watchdog timer/real-time clock/12-bit interval timer clock) 15 khz (typ.): v dd = 2.4 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.04167 s (high-speed on-chip oscillator: f hoco = 48 mhz /f ih = 24 mhz operation) 0.04167 s (pll clock: f pll = 48 mhz /f ih = 24 mhz note 2 operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) ? 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 22 38 cmos i/o 16 (n-ch o.d. i/o [v dd withstand voltage]: 5) 28 (n-ch o.d. i/o [v dd withstand voltage]: 6) cmos input 3 5 cmos output ? 1 n-ch open-drain i/o (6 v tolerance) 3 4 timer 16-bit timer 4 channel watchdog timer 1 channel real-time clock (rtc) 1 channel note 3 12-bit interval timer (it) 1 channel timer output 4 channels (pwm output: 3) note 4 rtc output ? 1 ? 1 hz (subsystem clock: f sub = 32.768 khz) notes 1. in the case of the 5.5 kb, this is about 4.5 kb when the self-programming function is used. (for details, see chapter 3 in the rl78/g1c user?s manual: hardware ) 2. in the pll clock 48 mhz operation, the system clock is 2/4/8 dividing ratio. 3. in 32-pin products, this channel can only be used for the constant-period interrupt function based on the low-speed on-chip oscillator clock (f il ). 4. the number of pwm outputs varies depending on the setti ng of channels in use (the number of masters and slaves). ( 6.9.3 operation as multiple pwm output function in the rl78/g1c user?s manual: hardware ) caution this outline describes the functions at the time when peripheral i/o redirection register (pior) is set to 00h.
rl78/g1c 1. outline page 16 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2/2) item 32-pin 48-pin r5f10jbc r5f10kbc r5f10jgc r5f10kgc clock output/buzzer output 2 2 ? 2.93 khz, 5.86 khz, 11.7 khz, 1.5 mhz, 3 mhz, 6 mhz, 12 mhz (main system clock: f main = 24 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 8 channels 9 channels serial interface csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel usb host controller 2 channels ? 2 channels ? function controller 1 channel multiplier and divider/multiply-accumulator ? multiplier: 16 bits 16 bits = 32 bits (unsigned or signed) ? divider: 32 bits 32 bits = 32 bits (unsigned) ? multiply-accumulator:16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels vectored interrupt sources internal 20 20 external 8 10 key interrupt ? 6 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 v (typ.) ? power-down-reset: 1.50 v (typ.) voltage detector 2.45 v to 4.06 v (9 stages) on-chip debug function provided power supply voltage v dd = 2.4 to 5.5 v operating ambient temperature t a = ? 40 to +85 c (a: consumer applications), t a = ? 40 to +105c (g: industrial applications) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip de bug emulator.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 17 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2. electrical specifications (a: t a = -40 to +85 c) this chapter describes the electrical specifications for the products "a: consumer applications (t a = -40 to +85 c)". the target products a: consumer applications ; t a = -40 to +85 c r5f10jbcana, r5f10jbcaf p, r5f10jgcana, r5f10jgcafb, r5f10kbcana, r5f10kbcaf p, r5f10kgcana, r5f10kgcafb g: industrial applications ; when using t a = -40 to +105 c specification products at t a = -40 to +85 c. r5f10jbcgna, r5f10jbcgf p, r5f10jgcgna, r5f10jgcgfb, r5f10kbcgna, r5f10kbcgf p, r5f10kgcgna, r5f10kgcgfb cautions 1. the rl78 microcontrollers has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. the pins mounted depend on the product. refer to 2.1 port function to 2.2.1 with functions for each product in the rl78/g1c user?s manual: hardware.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 18 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to +6.5 v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v uv dd pin input voltage v iuvdd uv dd ? 0.3 to v dd +0.3 v input voltage v i1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p70 to p75, p120 to p124, p137, p140, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ? 0.3 to +6.5 v v i3 udp0, udm0, udp1, udm1 ? 0.3 to +6.5 v v i4 uv bus ? 0.3 to +6.5 v output voltage v o1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p130, p140 ? 0.3 to v dd +0.3 note 2 v v o2 udp0, udm0, udp1, udm1 ? 0.3 to +6.5 v analog input voltage v ai1 ani16, ani17, ani19 ? 0.3 to v dd +0.3 and ? 0.3 to av ref (+) +0.3 notes 2, 3 v v ai2 ani0 to ani7 ? 0.3 to v dd +0.3 and ? 0.3 to av ref (+) +0.3 notes 2, 3 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. av ref (+): the + side reference voltage of the a/d converter. this can be selected from av refp , the internal reference voltage (1.45 v), and v dd . 3. v ss : reference voltage
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 19 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit output current, high i oh1 per pin p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 ? 40 ma total of all pins ? 170 ma p00, p01, p40, p41, p120, p130, p140 ? 70 ma p14 to p17, p30, p31, p50, p51, p70 to p75 ? 100 ma i oh2 per pin p20 to p27 ? 0.5 ma total of all pins ? 2 ma output current, low i ol1 per pin p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p130, p140 40 ma total of all pins 170 ma p00, p01, p40, p41, p120, p130, p140 70 ma p14 to p17, p30, p31, p50, p51, p60 to p63, p70 to p75 100 ma i ol2 per pin p20 to p27 1 ma total of all pins 5 ma operating ambient temperature t a in normal operation mode ? 40 to +85 c in flash memory programming mode storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 20 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.2 oscillator characteristics 2.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz xt1 clock oscillation frequency (f xt ) note crystal resonator 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, ch eck the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. determine the oscilla tion stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator and xt1 oscillator, refer to 5.4 system clock oscillator in the rl78/g1c user?s manual: hardware . 2.2.2 on-chip oscillator characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f hoco 1 48 mhz high-speed on-chip oscillator clock frequency accuracy ? 20 to +85 c ? 1.0 +1.0 % ? 40 to ? 20 c ? 1.5 +1.5 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h/010c2h) and bits 0 to 2 of hocodiv register. 2. this indicates the oscillator characteristics only. refer to ac characteristics for instruction execution time.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 21 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.2.3 pll oscillator characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit pll input frequency note f pllin high-speed system clock 6.00 16.00 mhz pll output frequency note f pll 48.00 mhz lock up time from pll output enable to stabilization of the output frequency 40.00 s interval time from pll stop to pll re-operation setteing wait time 4.00 s setting wait time from after pll input clock stabilization and pll setting is fixed to start setting wait time required 1.00 s note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 22 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 2.4 v v dd 5.5 v ? 10.0 note 2 ma total of p00, p01, p40, p41, p120, p130, p140 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 55.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma 2.4 v v dd < 2.7 v ? 5.0 ma total of p14 to p17, p30, p31, p50, p51, p70 to p75 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 80.0 ma 2.7 v v dd < 4.0 v ? 19.0 ma 2.4 v v dd < 2.7 v ? 10.0 ma total of all pins (when duty 70% note 3 ) 2.4 v v dd 5.5 v ? 135.0 ma i oh2 per pin for p20 to p27 2.4 v v dd 5.5 v ? 0.1 note 2 ma total of all pins (when duty 70% note 3 ) 2.4 v v dd 5.5 v ? 1.5 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00, p01, p30, and p74 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 23 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 2.4v v dd 5.5 v 20.0 note 2 ma per pin for p60 to p63 2.4v v dd 5.5 v 20.0 note 2 ma total of p00, p01, p40, p41, p120, p130, p140 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 70.0 ma 2.7 v v dd < 4.0 v 15.0 ma 2.4 v v dd < 2.7 v 9.0 ma total of p14 to p17, p30, p31, p50, p51, p60 to p63, p70 to p75 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 80.0 ma 2.7 v v dd < 4.0 v 35.0 ma 2.4 v v dd < 2.7 v 20.0 ma total of all pins (when duty 70% note 3 ) 2.4v v dd 5.5 v 150.0 ma i ol2 per pin for p20 to p27 2.4v v dd 5.5 v 0.4 note 2 ma total of all pins (when duty 70% note 3 ) 2.4v v dd 5.5 v 5.0 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pins = (10.0 0.7)/(80 0.01) ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 24 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p140 normal input buffer 0.8v dd v dd v v ih2 p00, p01, p30, p50 ttl input buffer 4.0 v v dd 5.5 v 2.2 v dd v ttl input buffer 3.3 v v dd < 4.0 v 2.0 v dd v ttl input buffer 2.4 v v dd < 3.3 v 1.5 v dd v v ih3 p20 to p27 0.7v dd v dd v v ih4 p60 to p63 0.7v dd 6.0 v v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v input voltage, low v il1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p140 normal input buffer 0 0.2v dd v v il2 p00, p01, p30, p50 ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 3.3 v v dd < 4.0 v 0 0.5 v ttl input buffer 2.4 v v dd < 3.3 v 0 0.32 v v il3 p20 to p27 0 0.3v dd v v il4 p60 to p63 0 0.3v dd v v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v caution the maximum value of v ih of pins p00, p01, p30, and p74 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of the port pins.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 25 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 4.0 v v dd 5.5 v, i oh1 = ? 10.0 ma v dd ? 1.5 v 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd 5.5 v, i oh1 = ? 2.0 ma v dd ? 0.6 v 2.4 v v dd 5.5 v, i oh1 = ? 1.5 ma v dd ? 0.5 v v oh2 p20 to p27 2.4 v v dd 5.5 v, i oh2 = ? 100 a v dd ? 0.5 v output voltage, low v ol1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 4.0 v v dd 5.5 v, i ol1 = 20.0 ma 1.3 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v 2.4 v v dd 5.5 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p27 2.4 v v dd 5.5 v, i ol2 = 400 a 0.4 v v ol3 p60 to p63 4.0 v v dd 5.5 v, i ol1 = 20.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v 2.4 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v caution p00, p01, p30, and p74 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 26 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit input leakage current, high i lih1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p137, p140, reset v i = v dd 1 a i lih2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in input port or external clock input 1 a in resonator connection 10 a input leakage current, low i lil1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p137, p140, reset v i = v ss ? 1 a i lil2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in input port or external clock input ? 1 a in resonator connection ? 10 a on-chip pll-up resistance r u p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p140 v i = v ss , in input port 10 20 100 k remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 27 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.3.2 supply current characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode note 6 f hoco = 48 mhz f ih = 24 mhz note 3 basic operation v dd = 5.0 v 1.7 ma v dd = 3.0 v 1.7 ma normal operation v dd = 5.0 v 3.7 5.5 ma v dd = 3.0 v 3.7 5.5 ma f hoco = 24 mhz note 5 f ih = 12 mhz note 3 normal operation v dd = 5.0 v 2.3 3.2 ma v dd = 3.0 v 2.3 3.2 ma f hoco = 12 mhz note 5 f ih = 6 mhz note 3 normal operation v dd = 5.0 v 1.6 2.0 ma v dd = 3.0 v 1.6 2.0 ma f hoco = 6 mhz note 5 f ih = 3 mhz note 3 normal operation v dd = 5.0 v 1.2 1.5 ma v dd = 3.0 v 1.2 1.5 ma hs (high-speed main) mode note 6 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.0 4.6 ma resonator connection 3.2 4.8 ma f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.0 4.6 ma resonator connection 3.2 4.8 ma f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 1.9 2.7 ma resonator connection 1.9 2.7 ma f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 1.9 2.7 ma resonator connection 1.9 2.7 ma hs (high-speed main) mode (pll operation) note 6 f pll = 48 mhz, f clk = 24 mhz note 2 normal operation v dd = 5.0 v 4.0 5.9 ma v dd = 3.0 v 4.0 5.9 ma f pll = 48 mhz, f clk = 12 mhz note 2 normal operation v dd = 5.0 v 2.6 3.6 ma v dd = 3.0 v 2.6 3.6 ma f pll = 48 mhz, f clk = 6 mhz note 2 normal operation v dd = 5.0 v 1.9 2.4 ma v dd = 3.0 v 1.9 2.4 ma subsystem clock operation f sub = 32.768 khz note 4 t a = ? 40 c normal operation resonator connection 4.1 4.9 a square wave input 4.2 5.0 a f sub = 32.768 khz note 4 t a = +25 c normal operation square wave input 4.1 4.9 a resonator connection 4.2 5.0 a f sub = 32.768 khz note 4 t a = +50 c normal operation square wave input 4.2 5.5 a resonator connection 4.3 5.6 a f sub = 32.768 khz note 4 t a = +70 c normal operation square wave input 4.2 6.3 a resonator connection 4.3 6.4 a f sub = 32.768 khz note 4 t a = +85 c normal operation square wave input 4.8 7.7 a resonator connection 4.9 7.8 a ( notes and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 28 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd , or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-s peed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the rtc, 12-bit interval timer, and watchdog timer. 5. when operating frequency setting of option byte = 48 mhz. when f hoco is divided by hocodiv. when rdiv[1:0] = 00 (divided by 2: default). 6. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 24 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remarks 1. f hoco : high-speed on-chip oscillator clock frequency (max. 48 mhz) 2. f ih : main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (max. 24 mhz) 3. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 4. f pll : pll oscillation frequency 5. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 6. f clk : cpu/peripheral hardware clock frequency 7. except subsystem clock operation, temperature condition of the typ. value is t a = 25 c.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 29 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 9 f hoco = 48 mhz f ih = 24 mhz note 4 v dd = 5.0 v 0.67 1.25 ma v dd = 3.0 v 0.67 1.25 ma f hoco = 24 mhz note 7 f ih = 12 mhz note 4 v dd = 5.0 v 0.50 0.86 ma v dd = 3.0 v 0.50 0.86 ma f hoco = 12 mhz note 7 f ih = 6 mhz note 4 v dd = 5.0 v 0.41 0.67 ma v dd = 3.0 v 0.41 0.67 ma f hoco = 6 mhz note 7 f ih = 3 mhz note 4 v dd = 5.0 v 0.37 0.58 ma v dd = 3.0 v 0.37 0.58 ma hs (high-speed main) mode note 9 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.28 1.00 ma resonator connection 0.45 1.17 ma f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.28 1.00 ma resonator connection 0.45 1.17 ma f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.19 0.60 ma resonator connection 0.26 0.67 ma f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.19 0.60 ma resonator connection 0.26 0.67 ma hs (high-speed main) mode (pll operation) note 9 f pll = 48 mhz, f clk = 24 mhz note 3 v dd = 5.0 v 0.91 1.52 ma v dd = 3.0 v 0.91 1.52 ma f pll = 48 mhz, f clk = 12 mhz note 3 v dd = 5.0 v 0.85 1.28 ma v dd = 3.0 v 0.85 1.28 ma f pll = 48 mhz, f clk = 6 mhz note 3 v dd = 5.0 v 0.82 1.15 ma v dd = 3.0 v 0.82 1.15 ma subsystem clock operation f sub = 32.768 khz note 5 t a = ? 40 c square wave input 0.25 0.57 a resonator connection 0.44 0.76 a f sub = 32.768 khz note 5 t a = +25 c square wave input 0.30 0.57 a resonator connection 0.49 0.76 a f sub = 32.768 khz note 5 t a = +50 c square wave input 0.33 1.17 a resonator connection 0.63 1.36 a f sub = 32.768 khz note 5 t a = +70 c square wave input 0.46 1.97 a resonator connection 0.76 2.16 a f sub = 32.768 khz note 5 t a = +85 c square wave input 0.97 3.37 a resonator connection 1.16 3.56 a i dd3 note 6 stop mode note 8 t a = ? 40 c 0.18 0.50 a t a = +25 c 0.23 0.50 a t a = +50 c 0.26 1.10 a t a = +70 c 0.29 1.90 a t a = +85 c 0.90 3.30 a ( notes and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 30 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, usb 2.0 host/function module, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip osc illator and high-speed system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rtc, 12-bit interval timer, and watchdog timer. 7. when operating frequency setting of option byte = 48 mhz. when f hoco is divided by hocodiv. when rdiv[1:0] = 00 (divided by 2: default). 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. 9. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 24 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remarks 1. f hoco : high-speed on-chip oscillator clock frequency (max. 48 mhz) 2. f ih : main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (max. 24 mhz) 3. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 4. f pll : pll oscillation frequency 5. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 6. f clk : cpu/peripheral hardware clock frequency 7. except subsystem clock operation, temperature condition of the typ. value is t a = 25 c.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 31 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit low-speed on-chip oscillator operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating current i adc notes 1, 6 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref note 1 75.0 a temperature sensor operating current i tmps note 1 75.0 a lvd operating current i lvd notes 1, 7 0.08 a self-programming operating current i fsp notes 1, 9 2.00 12.20 ma bgo operating current i bgo notes 1, 8 2.00 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 10 0.50 1.06 ma the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 1.20 1.62 ma csi operation 0.70 0.84 ma ( notes and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 32 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit usb operating current i usbh note 11 during usb communication operation under the following settings and conditions (v dd = 5.0 v, t a = +25 c): ? the internal power supply for the usb is used. ? x1 oscillation frequency (f x ) = 12 mhz, pll oscillation frequency (f pll ) = 48 mhz ? the host controller (via two ports) is set to operate in full-speed mode with four pipes (end points) used simultaneously. (pipe4: bulk out transfer (64 bytes), pipe5: bulk in transfer (64 bytes), pipe6: interrupt out transfer, pipe7: interrupt in transfer). ? the usb ports (two ports) are individually connected to a peripheral function via a 0.5 m usb cable. 9.0 ma i usbf note 11 during usb communication operation under the following settings and conditions (v dd = 5.0 v, t a = +25 c): ? the internal power supply for the usb is used. ? x1 oscillation frequency (f x ) = 12 mhz, pll oscillation frequency (f pll ) = 48 mhz ? the function controller is set to operate in full-speed mode with four pipes (end points) used simultaneously. (pipe4: bulk out transfer (64 bytes), pipe5: bulk in transfer (64 bytes), pipe6: interrupt out transfer, pipe7: interrupt in transfer). ? the usb port (one port) is connected to the host device via a 0.5 m usb cable. 2.5 ma i susp note 12 during suspended state under the following settings and conditions (v dd = 5.0 v, t a = +25 c): ? the function controller is set to full-speed mode (the udp0 pin is pulled up). ? the internal power supply for the usb is used. ? the system is set to stop mode (when the high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. when the watchdog timer is stopped.). ? the usb port (one port) is connected to the host device via a 0.5 m usb cable. 240 a ( notes and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 33 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. current flowing to v dd . 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (excluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer is in operation. 6. current flowing only to the a/d converter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 7. current flowing only to the lvd circuit. the current value of the rl78/g1c is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvd circuit operates in the operating, halt or stop mode. 8. current flowing only during data flash rewrite. 9. current flowing only during self programming. 10. for shift time to the snooze mode, see 19.3.3 snooze mode in the rl78/g1c user?s manual: hardware. 11. current consumed only by the usb module and the internal power supply for the usb. 12. includes the current supplied from the pull-up resistor of the udp0 pin to the pull-down resistor of the host device, in addition to the current consumed by this mcu during the suspended state. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 34 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.4 ac characteristics 2.4.1 basic operation (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s subsystem clock (f sub ) operation 2.4 v v dd 5.5 v 28.5 30.5 31.3 s in the self programming mode hs (high-speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s external system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz f exs 32 35 khz external system clock input high-level width, low-level width t exh , t exl 2.7 v v dd 5.5 v 24 ns 2.4 v v dd < 2.7 v 30 ns t exhs , t exls 13.7 s ti00 to ti03 input high-level width, low-level width t tih , t til 1/f mck +10 ns to00 to to03 output frequency f to high-speed main mode 4.0 v v dd 5.5 v 12 mhz 2.7 v v dd < 4.0 v 8 mhz 2.4 v v dd < 2.7 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl high-speed main mode 4.0 v v dd 5.5 v 16 mhz 2.7 v v dd < 4.0 v 8 mhz 2.4 v v dd < 2.7 v 4 mhz interrupt input high-level width, low-level width t inth , t intl intp0 to intp6, intp8, intp9 2.4 v v dd 5.5 v 1 s key interrupt input low-level width t kr kr0 to kr5 2.4 v v dd 5.5 v 250 ns reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of timer mode register 0n (tmr0n). n: channel number (n = 0 to 3))
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 35 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.04167 0.0625 0.05 cycle time t cy [s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk/exclks 1/f ex / 1/f exs t exl / t exls t exh / t exhs
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 36 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 ti/to timing ti00 to ti03 t til t tih to00 to to03 1/f to interrupt request input timing intp0 to intp6, intp8, intp9 t intl t inth key interrupt input timing kr0 to kr5 t kr reset input timing reset t rsl
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 37 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.5 peripheral functions characteristics 2.5.1 serial array unit (1) during communication at same potential (uart mode) (dedicated baud rate generator output) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 4.0 mbps note the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (during communication at same potential) user's device txdq rxdq rx tx rl78 microcontroller uart mode bit width (during communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq remarks 1. q: uart number (q = 0), g: pim and pom number (g = 5) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 38 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) during communication at same potential (csi mode) (master mode, sckp... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 2/f clk 2.7 v v dd 5.5 v 83.3 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 ? 7 ns 2.7 v v dd 5.5 v t kcy1 /2 ? 10 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 23 ns 2.7 v v dd 5.5 v 33 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd 5.5 v 10 ns delay time from sckp to sop output note 3 t kso1 c = 20 pf note 3 10 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. this specification is valid only when csi00?s peripheral i/o redirect function is not used. 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom numbers (g = 3, 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 39 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) during communication at same potential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01), m: unit number (m = 0), n: channel number (n = 0, 1), g: pim and pom numbers (g = 0, 3, 5, 7) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01)) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd 5.5 v 167 ns 2.4 v v dd 5.5 v 250 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 ? 12 ns 2.7 v v dd 5.5 v t kcy1 /2 ? 18 ns 2.4 v v dd 5.5 v t kcy1 /2 ? 38 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 44 ns 2.7 v v dd 5.5 v 44 ns 2.4 v v dd 5.5 v 75 ns sip hold time (from sckp ) note 2 t ksi1 19 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 25 ns
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 40 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (4) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time note 5 t kcy2 4.0 v v dd 5.5 v 20 mhz < f mck 8/f mck ns f mck 20 mhz 6/f mck ns 2.7 v v dd 5.5 v 16 mhz < f mck 8/f mck ns f mck 16 mhz 6/f mck ns 2.4 v v dd 5.5 v 6/f mck and 500 ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v t kcy2 /2 ? 7 ns 2.7 v v dd 5.5 v t kcy2 /2 ? 8 ns 2.4 v v dd 5.5 v t kcy2 /2 ? 18 ns sip setup time (to sckp ) note 1 t sik2 2.7 v v dd 5.5 v 1/f mck +20 ns 2.4 v v dd 5.5 v 1/f mck +30 ns sip hold time (from sckp ) note 2 t ksi2 2.7 v v dd 5.5 v 1/f mck +31 ns 2.4 v v dd 5.5 v 1/f mck +31 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v v dd 5.5 v 2/f mck +44 ns 2.4 v v dd 5.5 v 2/f mck +75 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (p img) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01), m: unit number (m = 0), n: channel number (n = 0, 1), g: pim number (g = 0, 3, 5, 7) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01))
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 41 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 csi mode connection diagram (during communication at same potential) user's device sckp sop sck si sip so rl78 microcontroller csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01) 2. m: unit number, n: channel number (mn = 00, 01)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 42 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (5) during communication at same potential (simplified i 2 c mode) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit sclr clock frequency f scl 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1000 note 1 khz 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 400 note 1 khz 2.4 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 300 note 1 khz hold time when sclr = ?l? t low 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 475 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 ns 2.4 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 1550 ns hold time when sclr = ?h? t high 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 475 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 ns 2.4 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 1550 ns data setup time (reception) t su:dat 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1/f mck + 85 note 2 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note 2 ns 2.4 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 1/f mck + 230 note 2 ns data hold time (transmission) t hd:dat 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 0 305 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 355 ns 2.4 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 0 405 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). ( caution and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 43 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 simplified i 2 c mode mode connection diagram (during communication at same potential) user's device sdar sclr sda scl v dd r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01), g: pim number (g = 5), h: pom number (h = 3, 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0), n: channel number (n = 0, 1), mn = 00, 01)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 44 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (6) communication at different potential (2.5 v, 3 v) (uart mode) (1/2) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate reception 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 4.0 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 4.0 mbps 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 4.0 mbps notes 1. use it with v dd v b . 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0), g: pim and pom number (g = 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 45 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (6) communication at different potential (2.5 v, 3 v) (uart mode) (2/2) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate transmission 4.0 v v dd 5.5 v, note 1 bps 2.7 v v b 4.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 mbps 2.7 v v dd < 4.0 v note 3 bps 2.3 v v b 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps 2.4 v v dd < 3.3 v notes 5, 6 bps 1.6 v v b 2.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 7 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v maximum transfer rate = 1 [bps] { ? cb rb ln (1 ? 2.2 vb )} 3 1 transfer rate 2 ? { ? cb rb ln (1 ? 2.2 vb )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference between the transmission and reception sides. 2. this value as an example is calculated when the conditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v maximum transfer rate = 1 [bps] { ? cb rb ln (1 ? 2.0 vb )} 3 1 transfer rate 2 ? { ? cb rb ln (1 ? 2.0 vb )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference between the transmission and reception sides. 4. this value as an example is calculated when the conditions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. use it with v dd v b .
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 46 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 6. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v v dd < 3.3 v and 1.6 v v b 2.0 v maximum transfer rate = 1 [bps] { ? cb rb ln (1 ? 1.5 vb )} 3 1 transfer rate 2 ? { ? cb rb ln (1 ? 1.5 vb )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference between the transmission and reception sides. 7. this value as an example is calculated when the conditions described in the ?conditions? column are met. refer to note 6 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. uart mode connection diagram (during communication at different potential) user's device txdq rxdq rx tx v b r b rl78 microcontroller
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 47 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate remarks 1. r b [ ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0), g: pim and pom number (g = 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 48 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (7) communication at different potential (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 2/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 200 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 300 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 ? 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 120 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 ? 7 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 10 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 58 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 121 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 60 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 130 ns sip setup time (to sckp ) note 2 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 23 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 33 ns sip hold time (from sckp ) note 2 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 ns delay time from sckp to sop output note 2 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( caution and remark are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 49 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. r b [ ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00) 4. this value is valid only when csi00?s peripheral i/o redirect function is not used.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 50 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/2) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 300 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 500 ns 2.4 v v dd < 3.3 v, 2.4 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 1150 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 75 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 458 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 12 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 18 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 50 ns cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. use it with v dd v b . (remarks are listed two pages after the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 51 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/2) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 81 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 479 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 19 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 100 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 483 ns sip setup time (to sckp ) note 2 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 44 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 110 ns sip hold time (from sckp ) note 2 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 19 ns delay time from sckp to sop output note 2 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 25 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 25 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 25 ns ( notes , cautions and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 52 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. use it with v dd v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) v b r b user's device sckp sop sck si sip so v b r b rl78 microcontroller remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number , n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 53 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp remarks 1. p: csi number (p = 00), m: unit number, n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 2. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 54 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time note 1 t kcy2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 20 mhz < f mck 24 mhz 12/f mck ns 8 mhz < f mck 20 mhz 10/f mck ns 4 mhz < f mck 8 mhz 8/f mck ns f mck 4 mhz 6/f mck ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 20 mhz < f mck 24 mhz 16/f mck ns 16 mhz < f mck 20 mhz 14/f mck ns 8 mhz < f mck 16 mhz 12/f mck ns 4 mhz < f mck 8 mhz 8/f mck ns f mck 4 mhz 6/f mck ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 20 mhz < f mck 24 mhz 36/f mck ns 16 mhz < f mck 20 mhz 32/f mck ns 8 mhz < f mck 16 mhz 26/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 10/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 ? 12 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 ? 18 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 t kcy2 /2 ? 50 ns sip setup time (to sckp ) note 3 t sik2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 1/f mck + 20 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 1/f mck + 20 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 1/f mck + 30 ns sip hold time (from sckp ) note 4 t ksi2 1/f mck + 31 ns delay time from sckp to sop output note 5 t kso2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 120 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 214 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 2/f mck + 573 ns notes 1. transfer rate in the snooze mode: max. 1 mbps 2. use it with v dd v b . 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( caution and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 55 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) user's device sckp sop sck si sip so v b r b rl78 microcontroller remarks 1. r b [ ]:communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number, n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 56 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp remarks 1. p: csi number (p = 00), m: unit number, n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 2. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 57 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit sclr clock frequency f scl 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1000 note 1 khz 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1000 note 1 khz 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 400 note 1 khz 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 400 note 1 khz 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 300 note 1 khz hold time when sclr = ?l? t low 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 475 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 475 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1150 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 1150 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 1550 ns hold time when sclr = ?h? t high 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 245 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 200 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 675 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 600 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 610 ns ( notes , caution and remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 58 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit data setup time (reception) t su:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 3 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 3 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 190 note 3 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 note 3 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v notes 2 , c b = 100 pf, r b = 5.5 k 1/f mck + 190 note 3 ns data hold time (transmission) t hd:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 0 305 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 0 305 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 355 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 0 355 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 0 405 ns notes 1. the value must also be equal to or less than f mck /4. 2. use it with v dd v b . 3. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 59 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 simplified i 2 c mode connection diagram (during communication at different potential) user's device sdar sclr sda scl v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ]:communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00), g: pim, pom number (g = 0, 3, 5, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 60 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.5.2 serial interface iica (1) i 2 c standard mode (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. scla0 clock frequency f scl standard mode: f clk 1 mhz 2.7 v v dd 5.5 v 0 100 khz 2.4 v v dd 5.5 v 0 100 khz setup time of restart condition t su:sta 2.7 v v dd 5.5 v 4.7 s 2.4 v v dd 5.5 v 4.7 s hold time note 1 t hd:sta 2.7 v v dd 5.5 v 4.0 s 2.4 v v dd 5.5 v 4.0 s hold time when scla0 = ?l? t low 2.7 v v dd 5.5 v 4.7 s 2.4 v v dd 5.5 v 4.7 s hold time when scla0 = ?h? t high 2.7 v v dd 5.5 v 4.0 s 2.4 v v dd 5.5 v 4.0 s data setup time (reception) t su:dat 2.7 v v dd 5.5 v 250 s 2.4 v v dd 5.5 v 250 s data hold time (transmission) note 2 t hd:dat 2.7 v v dd 5.5 v 0 3.45 s 2.4 v v dd 5.5 v 0 3.45 s setup time of stop condition t su:sto 2.7 v v dd 5.5 v 4.0 s 2.4 v v dd 5.5 v 4.0 s bus-free time t buf 2.7 v v dd 5.5 v 4.7 s 2.4 v v dd 5.5 v 4.7 s notes 1. the first clock pulse is generated after this period when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bit 1 (pior1) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of cb (communication line capacitance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 61 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) i 2 c fast mode (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. scla0 clock frequency f scl fast mode: f clk 3.5 mhz 2.7 v v dd 5.5 v 0 400 khz 2.4 v v dd 5.5 v 0 400 khz setup time of restart condition t su:sta 2.7 v v dd 5.5 v 0.6 s 2.4 v v dd 5.5 v 0.6 s hold time note 1 t hd:sta 2.7 v v dd 5.5 v 0.6 s 2.4 v v dd 5.5 v 0.6 s hold time when scla0 = ?l? t low 2.7 v v dd 5.5 v 1.3 s 2.4 v v dd 5.5 v 1.3 s hold time when scla0 = ?h? t high 2.7 v v dd 5.5 v 0.6 s 2.4 v v dd 5.5 v 0.6 s data setup time (reception) t su:dat 2.7 v v dd 5.5 v 100 ns 2.4 v v dd 5.5 v 100 ns data hold time (transmission) note 2 t hd:dat 2.7 v v dd 5.5 v 0 0.9 s 2.4 v v dd 5.5 v 0 0.9 s setup time of stop condition t su:sto 2.7 v v dd 5.5 v 0.6 s 2.4 v v dd 5.5 v 0.6 s bus-free time t buf 2.7 v v dd 5.5 v 1.3 s 2.4 v v dd 5.5 v 1.3 s notes 1. the first clock pulse is generated after this period when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bit 1 (pior1) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of cb (communication line capacitance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. fast mode: c b = 320 pf, r b = 1.1 k
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 62 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) i 2 c fast mode plus (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. scla0 clock frequency f scl fast mode plus: f clk 10 mhz 2.7 v v dd 5.5 v 0 1000 khz setup time of restart condition t su:sta 2.7 v v dd 5.5 v 0.26 s hold time note 1 t hd:sta 2.7 v v dd 5.5 v 0.26 s hold time when scla0 = ?l? t low 2.7 v v dd 5.5 v 0.5 s hold time when scla0 = ?h? t high 2.7 v v dd 5.5 v 0.26 s data setup time (reception) t su:dat 2.7 v v dd 5.5 v 50 ns data hold time (transmission) note 2 t hd:dat 2.7 v v dd 5.5 v 0 0.45 s setup time of stop condition t su:sto 2.7 v v dd 5.5 v 0.26 s bus-free time t buf 2.7 v v dd 5.5 v 0.5 s notes 1. the first clock pulse is generated after this period when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bit 1 (pior1) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of cb (communication line capacitance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. fast mode plus: c b = 120 pf, r b = 1.1 k iica serial transfer timing t low t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scla0 sdaa0
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 63 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.5.3 usb (1) electrical specifications (t a = ? 40 to +85 c, 3.0 v uv dd 3.6 v, 3.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit uv dd uv dd input voltage characteristic uv dd v dd = 3.0 to 5.5 v, pxxcon = 1, vdduseb = 0 (uv dd v dd ) 3.0 3.3 3.6 v uv dd output voltage characteristic uv dd v dd = 4.0 to 5.5 v, pxxcon = vdduseb = 1 3.0 3.3 3.6 v uv bus uv bus input voltage characteristic uv bus function 4.35 (4.02 note ) 5.00 5.25 v host 4.75 5.00 5.25 v note value of instantaneous voltage (t a = ? 40 to +85 c, 3.0 v uv dd 3.6 v, 3.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit udpi/udmi pins input characteristic (fs/ls receiver) input voltage v ih 2.0 v v il 0.8 v difference input sensitivity v di | udp voltage ? udm voltage | 0.2 v difference common mode range v cm 0.8 2.5 v udpi/udmi pins output characteristic (fs driver) output voltage v oh i oh = ? 200 a 2.8 3.6 v v ol i ol = 2.4 ma 0 0.3 v transi-ti on time rising t fr rising: from 10% to 90 % of amplitude, falling: from 90% to 10 % of amplitude, cl = 50 pf 4 20 ns falling t ff 4 20 ns matching (tfr/tff) v frfm 90 111.1 % crossover voltage v fcrs 1.3 2.0 v output impedance z drv uv dd voltage = 3.3 v, pin voltage = 1.65 v 28 44 udpi/udmi pins output characteristic (ls driver) output voltage v oh 2.8 3.6 v v ol 0 0.3 v transi-ti on time rising t lr rising: from 10% to 90 % of amplitude, falling: from 90% to 10 % of amplitude, cl = 200 to 600 pf when the host controller function is selected: the udmi pin (i = 0, 1) is pulled up via 1.5 k . when the function controller function is selected: the udp0 and udm0 pins are individually pulled down via 15 k 75 300 ns falling t lf 75 300 ns matching (tfr/tff) note v ltfm 80 125 % crossover voltage note v lcrs 1.3 2.0 v udpi/udmi pins pull-up, pull-down pull-down resistor r pd 14.25 24.80 k pull-up resistor (i = 0 only) idle r pui 0.9 1.575 k recep-t ion r pua 1.425 3.09 k uv bus uv bus pull-down resistor r vbus uv bus voltage = 5.5 v 1000 k uv bus input voltage v ih 3.20 v v il 0.8 v note excludes the first signal transition from the idle state. remark i = 0, 1
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 64 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 timing of udpi and udmi udpi udmi 90 % 90 % 10 % 10 % v crs (crossover voltage) t r t f (2) bc standard (t a = ? 40 to +85 c, 3.0 v uv dd 3.6 v, 3.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit usb standard bc1.2 udpi sink current i dp_sink 25 175 a udmi sink current i dm_sink 25 175 a dcd source current i dp_src 7 13 a dedicated charging port resistor r dcp_dat 0 v < udp/udm voltage < 1.0 v 200 data detection voltage v dat_ref 0.25 0.4 v udpi source voltage v dp_src output current 250 a 0.5 0.7 v udmi source voltage v dm_src output current 250 a 0.5 0.7 v remark i = 0, 1
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 65 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) bc option standard (host) (t a = ? 40 to +85 c, 4.75 v uv bus 5.25 v, 3.0 v uv dd 3.6 v, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit udpi output voltage (uv bus divider ratio) ? vdouei = 1 vdseli [3:0] (i = 0, 1) 1000 v p20 38 40 42 % uv bus 1001 v p27 51.6 53.6 55.6 % uv bus 1010 v p20 38 40 42 % uv bus 1100 v p33 60 66 72 % uv bus udmi output voltage (uv bus divider ratio) ? vdouei = 1 vdseli [3:0] (i = 0, 1) 1000 v m20 38 40 42 % uv bus 1001 v m20 38 40 42 % uv bus 1010 v m27 51.6 53.6 55.6 % uv bus 1100 v m33 60 66 72 % uv bus udpi comparing voltage note 1 (uv bus divider ratio) ? vdouei = 1 ? cusdetei = 1 vdseli [3:0] (i = 0, 1) 1000 v hdetp_up0 the rise of pin voltage detection voltage 56.2 % uv bus v hdetp_dwn0 the fall of pin voltage detection voltage 29.4 % uv bus 1001 v hdetp_up1 the rise of pin voltage detection voltage 60.5 % uv bus v hdetp_dwn1 the fall of pin voltage detection voltage 45.0 % uv bus 1010 v hdetp_up2 the rise of pin voltage detection voltage 56.2 % uv bus v hdetp_dwn2 the fall of pin voltage detection voltage 29.4 % uv bus udmi comparing voltage note 1 (uv bus divider ratio) ? vdouei = 1 ? cusdetei = 1 vdseli [3:0] (i = 0, 1) 1000 v hdetm_up0 the rise of pin voltage detection voltage 56.2 % uv bus v hdetm_dwn0 the fall of pin voltage detection voltage 29.4 % uv bus 1001 v hdetm_up1 the rise of pin voltage detection voltage 56.2 % uv bus v hdetm_dwn1 the fall of pin voltage detection voltage 29.4 % uv bus 1010 v hdetm_up2 the rise of pin voltage detection voltage 60.5 % uv bus v hdetm_dwn2 the fall of pin voltage detection voltage 45.0 % uv bus udpi pull-up detection note 2 connect detection with the full speed function (pull-up resistor) 1000 r hdet_pull in full-speed mode, the power supply voltage range of pull-up resistors connected to the usb function module is between 3.0 v and 3.6 v. 1.575 k 1001 1010 udmi pull-up detection note 2 connect detection with the low-speed (pull-up resistor) 1000 r hdet_pull in low-speed mode, the power supply voltage range of pull-up resistors connected to the usb function module is between 3.0 v and 3.6 v. 1.575 k 1001 1010 udmi sink current detection note 2 connect detection with the bc1.2 portable device (sink resistor) 1000 i hdet_sink 25 a 1001 1010 notes 1. if the voltage output from udpi or udmi (i = 0, 1) exceeds the range of the max and min values prescribed in this specification, dpcusdeti (bit 8) and dmcusdeti (bit 9) of the usbbcopti register are set to 1. 2. if the pull-up resistance or sink current prescribed in this specification is applied to udpi or udmi (i = 0, 1), dpcusdeti (bit 8) and dmcusdeti (bit 9) of the usbbcopti register are set to 1. remark i = 0, 1
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 66 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (4) bc option standard (function) (t a = ? 40 to +85 c, 4.35 v uv bus 5.25 v, 3.0 v uv dd 3.6 v, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit udpi/udmi input reference voltage (uv bus divider ratio) ? vdouei = 0 (i = 0)) vdseli [3:0] (i = 0) 0000 v ddet0 27 32 37 % uv bus 0001 v ddet1 29 34 39 % uv bus 0010 v ddet2 32 37 42 % uv bus 0011 v ddet3 35 40 45 % uv bus 0100 v ddet4 38 43 48 % uv bus 0101 v ddet5 41 46 51 % uv bus 0110 v ddet6 44 49 54 % uv bus 0111 v ddet7 47 52 57 % uv bus 1000 v ddet8 51 56 61 % uv bus 1001 v ddet9 55 60 65 % uv bus 1010 v ddet10 59 64 69 % uv bus 1011 v ddet11 63 68 73 % uv bus 1100 v ddet12 67 72 77 % uv bus 1101 v ddet13 71 76 81 % uv bus 1110 v ddet14 75 80 85 % uv bus 1111 v ddet15 79 84 89 % uv bus
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 67 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.6 analog characteristics 2.6.1 a/d converter characteristics classification of a/d converter characteristics input channel reference voltage reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani7 refer to 2.6.1 (1) . refer to 2.6.1 (3) . refer to 2.6.1 (4) . ani16, ani17, ani19 refer to 2.6.1 (2) . internal reference voltage temperature sensor output voltage refer to 2.6.1 (1) . ? (1) when av ref (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani2 to ani7, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +85 c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 1.2 3.5 lsb conversion time t conv 10-bit resolution target pin: ani2 to ani7 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 0.25 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 1.5 lsb analog input voltage v ain ani2 to ani7 0 av refp v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 4 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v ( notes are listed on the next page.)
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 68 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . 4. refer to 2.6.2 temperature sensor/internal reference voltage characteristics .
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 69 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani16, ani17, ani19 (t a = ? 40 to +85 c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage (? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 1.2 5.0 lsb conversion time t conv 10-bit resolution target ani pin: ani16, ani17, ani19 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 0.35 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 0.35 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 3.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.4 v v dd 5.5 v 2.00 lsb analog input voltage v ain ani16, ani17, ani19 0 av refp and v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd .
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 70 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target ani pin: ani0 to ani7, ani16, ani17, ani19, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error notes 1, 2 ainl 10-bit resolution 2.4 v v dd 5.5 v 1.2 7.0 lsb conversion time t conv 10-bit resolution target ani pin: ani0 to ani7, ani16, ani17, ani19 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target ani pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr full-scale error notes 1, 2 efs 10-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr integral linearity error note 1 ile 10-bit resolution 2.4 v v dd 5.5 v 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.4 v v dd 5.5 v 2.0 lsb analog input voltage v ain ani0 to ani7, ani16, ani17, ani19 0 v dd v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 3 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 2.6.2 temperature sensor/internal reference voltage characteristics .
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 71 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (4) when reference voltage (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani0 to ani7, ani16, ani17, ani19 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm note 4 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 8-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.4 v v dd 5.5 v 2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.4 v v dd 5.5 v 1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 2.6.2 temperature sensor/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage ( ? ) = av refm .
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 72 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/ c operation stabilization wait time t amp 5 s 2.6.3 por circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.47 1.51 1.55 v v pdr power supply fall time 1.46 1.50 1.54 v minimum pulse width note t pw 300 s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock (f main ) is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). t p w v por v pdr or 0.7 v su pply voltage (v dd )
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 73 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +85 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage supply voltage level v lvd0 power supply rise time 3.98 4.06 4.14 v power supply fall time 3.90 3.98 4.06 v v lvd1 power supply rise time 3.68 3.75 3.82 v power supply fall time 3.60 3.67 3.74 v v lvd2 power supply rise time 3.07 3.13 3.19 v power supply fall time 3.00 3.06 3.12 v v lvd3 power supply rise time 2.96 3.02 3.08 v power supply fall time 2.90 2.96 3.02 v v lvd4 power supply rise time 2.86 2.92 2.97 v power supply fall time 2.80 2.86 2.91 v v lvd5 power supply rise time 2.76 2.81 2.87 v power supply fall time 2.70 2.75 2.81 v v lvd6 power supply rise time 2.66 2.71 2.76 v power supply fall time 2.60 2.65 2.70 v v lvd7 power supply rise time 2.56 2.61 2.66 v power supply fall time 2.50 2.55 2.60 v v lvd8 power supply rise time 2.45 2.50 2.55 v power supply fall time 2.40 2.45 2.50 v minimum pulse width t lw 300 s detection delay time t ld 300 s
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 74 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +85 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvdc0 vpoc2, vpoc1, vpoc0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 v v lvdc1 lvis1, lvis0 = 1, 0 rising release reset voltage 2.56 2.61 2.66 v falling interrupt voltage 2.50 2.55 2.60 v v lvdc2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.66 2.71 2.76 v falling interrupt voltage 2.60 2.65 2.70 v v lvdc3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.68 3.75 3.82 v falling interrupt voltage 3.60 3.67 3.74 v v lvdd0 vpoc2, vpoc1, vpoc0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 v v lvdd1 lvis1, lvis0 = 1, 0 rising release reset voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvdd2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.96 3.02 3.08 v falling interrupt voltage 2.90 2.96 3.02 v v lvdd3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.98 4.06 4.14 v falling interrupt voltage 3.90 3.98 4.06 v 2.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 2.4 ac characteristics.
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 75 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 5.5 v note the value depends on the por detection voltage. when the voltage drops, the data is retained before a por reset is effected, but data is not retained when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 2.8 flash memory programming characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.4 v v dd 5.5 v 1 24 mhz number of code flash rewrites c erwr retaining years: 20 years t a = +85 c 1,000 times number of data flash rewrites notes 1, 2, 3 retaining years: 1 year t a = +25 c 1,000,000 retaining years: 5 years t a = +85 c 100,000 retaining years: 20 years t a = +85 c 10,000 notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renes as electronics self programming library. 3. these specifications show the characteristics of the flash memory and the results obtained from renesas electronics reliability testing. 2.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps
rl78/g1c 2. electrical specifications (a: t a = -40 to +85 c) page 76 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 2.10 timing specs for switching flash memory programming modes (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit 723 s + t hd processing time t su <4> 00h reception (toolrxd, tooltxd mode) <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until an external reset ends t hd : how long to keep the tool0 pin at the low level from when the external and internal resets end (excluding the processing time of the firmware to control the flash memory)
rl78/g1c 3. electric al specifications (g: t a = -40 to +105 ? c) page 77 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3. electrical specifications (g: t a = -40 to +105 ? c) this chapter describes the electrical specifications for the products "g: industrial applications (t a = -40 to +105 ?c)". the target products g: industrial applications ; t a = -40 to +105 ?c r5f10jbcgna, r5f10jbcgf p, r5f10jgcgna, r5f10jgcgfb, r5f10kbcgna, r5f10kbcgf p, r5f10kgcgna, r5f10kgcgfb cautions 1. the rl78 microcontrollers has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. the pins mounted depend on the product. refer to 2.1 port function to 2.2.1 with functions for each product in the rl78/g1c user?s manual: hardware. 3. please contact renesas electronics sales office for derating of operation under t a = +85 ? c to +105 ? c. derating is the systematic reduction of load for the sake of improved reliability. there are following differences between the products "g: industrial applications (t a = -40 to +105 ? c)" and the products ?a: consumer applications?. application parameter a: consumer applications g: industrial applications operating ambient temperature t a = -40 to +85? c t a = -40 to +105 ? c high-speed on-chip oscillator clock accuracy 2.4 v ? v dd ? 5.5 v ?1.0%@ t a = -20 to +85 ? c ?1.5%@ t a = -40 to -20 ? c 2.4 v ? v dd ? 5.5 v ?2.0%@ t a = +85 to +105? c ?1.0%@ t a = -20 to +85 ? c ?1.5%@ t a = -40 to -20 ? c serial array unit uart csi: f clk /2 (supporting 16 mbps), f clk /4 simplified i 2 c communication uart csi: f clk /4 simplified i 2 c communication iica normal mode fast mode fast mode plus normal mode fast mode remark the electrical characteristics of t he products g: industrial applications (t a = -40 to +105 ? c) are different from those of the products ?a: consumer applications?. for details, refer to 3.1 to 3.10.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 78 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to +6.5 v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v uv dd pin input voltage v iuvdd uv dd ? 0.3 to v dd +0.3 v input voltage v i1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p70 to p75, p120 to p124, p137, p140, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ? 0.3 to +6.5 v v i3 udp0, udm0, udp1, udm1 ? 0.3 to +6.5 v v i4 uv bus ? 0.3 to +6.5 v output voltage v o1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p130, p140 ? 0.3 to v dd +0.3 note 2 v v o2 udp0, udm0, udp1, udm1 ? 0.3 to +6.5 v analog input voltage v ai1 ani16, ani17, ani19 ? 0.3 to v dd +0.3 and ? 0.3 to av ref (+) +0.3 notes 2, 3 v v ai2 ani0 to ani7 ? 0.3 to v dd +0.3 and ? 0.3 to av ref (+) +0.3 notes 2, 3 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. av ref (+): the + side reference voltage of the a/d converter. this can be selected from av refp , the internal reference voltage (1.45 v), and v dd . 3. v ss : reference voltage
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 79 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit output current, high i oh1 per pin p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 ? 40 ma total of all pins ? 170 ma p00, p01, p40, p41, p120, p130, p140 ? 70 ma p14 to p17, p30, p31, p50, p51, p70 to p75 ? 100 ma i oh2 per pin p20 to p27 ? 0.5 ma total of all pins ? 2 ma output current, low i ol1 per pin p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p130, p140 40 ma total of all pins 170 ma p00, p01, p40, p41, p120, p130, p140 70 ma p14 to p17, p30, p31, p50, p51, p60 to p63, p70 to p75 100 ma i ol2 per pin p20 to p27 1 ma total of all pins 5 ma operating ambient temperature t a in normal operation mode ? 40 to +105 c in flash memory programming mode storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 80 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.2 oscillator characteristics 3.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz xt1 clock oscillation frequency (f xt ) note crystal resonator 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, ch eck the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. determine the oscilla tion stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator and xt1 oscillator, refer to 5.4 system clock oscillator in the rl78/g1c user?s manual: hardware . 3.2.2 on-chip oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f hoco 1 48 mhz high-speed on-chip oscillator clock frequency accuracy ? 20 to +85 c ? 1.0 +1.0 % ? 40 to ? 20 c ? 1.5 +1.5 % +85 to +105 c ? 2.0 +2.0 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h/010c2h) and bits 0 to 2 of hocodiv register. 2. this indicates the oscillator characteristics only. refer to ac characteristics for instruction execution time.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 81 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.2.3 pll oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit pll input frequency note f pllin high-speed system clock 6.00 16.00 mhz pll output frequency note f pll 48.00 mhz lock up time from pll output enable to stabilization of the output frequency 40.00 s interval time from pll stop to pll re-operation setteing wait time 4.00 s setting wait time from after pll input clock stabilization and pll setting is fixed to start setting wait time required 1.00 s note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 82 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.3 dc characteristics 3.3.1 pin characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 2.4 v v dd 5.5 v ? 3.0 note 2 ma total of p00, p01, p40, p41, p120, p130, p140 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma 2.4 v v dd < 2.7 v ? 5.0 ma total of p14 to p17, p30, p31, p50, p51, p70 to p75 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 19.0 ma 2.4 v v dd < 2.7 v ? 10.0 ma total of all pins (when duty 70% note 3 ) 2.4 v v dd 5.5 v -60.0 ma i oh2 per pin for p20 to p27 2.4 v v dd 5.5 v ? 0.1 note 2 ma total of all pins (when duty 70% note 3 ) 2.4 v v dd 5.5 v ? 1.5 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00, p01, p30, and p74 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 83 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 2.4v v dd 5.5 v 8.5 note 2 ma per pin for p60 to p63 2.4v v dd 5.5 v 15.0 note 2 ma total of p00, p01, p40, p41, p120, p130, p140 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 40.0 ma 2.7 v v dd < 4.0 v 15.0 ma 2.4 v v dd < 2.7 v 9.0 ma total of p14 to p17, p30, p31, p50, p51, p60 to p63, p70 to p75 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 40.0 ma 2.7 v v dd < 4.0 v 35.0 ma 2.4 v v dd < 2.7 v 20.0 ma total of all pins (when duty 70% note 3 ) 2.4v v dd 5.5 v 80.0 ma i ol2 per pin for p20 to p27 2.4v v dd 5.5 v 0.4 note 2 ma total of all pins (when duty 70% note 3 ) 2.4v v dd 5.5 v 5.0 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pins = (10.0 0.7)/(80 0.01) ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 84 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p140 normal input buffer 0.8v dd v dd v v ih2 p00, p01, p30, p50 ttl input buffer 4.0 v v dd 5.5 v 2.2 v dd v ttl input buffer 3.3 v v dd < 4.0 v 2.0 v dd v ttl input buffer 2.4 v v dd < 3.3 v 1.5 v dd v v ih3 p20 to p27 0.7v dd v dd v v ih4 p60 to p63 0.7v dd 6.0 v v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v input voltage, low v il1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p140 normal input buffer 0 0.2v dd v v il2 p00, p01, p30, p50 ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 3.3 v v dd < 4.0 v 0 0.5 v ttl input buffer 2.4 v v dd < 3.3 v 0 0.32 v v il3 p20 to p27 0 0.3v dd v v il4 p60 to p63 0 0.3v dd v v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v caution the maximum value of v ih of pins p00, p01, p30, and p74 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of the port pins.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 85 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd 5.5 v, i oh1 = ? 2.0 ma v dd ? 0.6 v 2.4 v v dd 5.5 v, i oh1 = ? 1.5 ma v dd ? 0.5 v v oh2 p20 to p27 2.4 v v dd 5.5 v, i oh2 = ? 100 a v dd ? 0.5 v output voltage, low v ol1 p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p130, p140 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v 2.4 v v dd 5.5 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p27 2.4 v v dd 5.5 v, i ol2 = 400 a 0.4 v v ol3 p60 to p63 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v 2.4 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v caution p00, p01, p30, and p74 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 86 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit input leakage current, high i lih1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p137, p140, reset v i = v dd 1 a i lih2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in input port or external clock input 1 a in resonator connection 10 a input leakage current, low i lil1 p00, p01, p14 to p17, p20 to p27, p30, p31, p40, p41, p50, p51, p60 to p63, p70 to p75, p120, p137, p140, reset v i = v ss ? 1 a i lil2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in input port or external clock input ? 1 a in resonator connection ? 10 a on-chip pll-up resistance r u p00, p01, p14 to p17, p30, p31, p40, p41, p50, p51, p70 to p75, p120, p140 v i = v ss , in input port 10 20 100 k remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 87 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.3.2 supply current characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) modffe note 6 f hoco = 48 mhz f ih = 24 mhz note 3 basic operation v dd = 5.0 v 1.7 ma v dd = 3.0 v 1.7 ma normal operation v dd = 5.0 v 3.7 5.8 ma v dd = 3.0 v 3.7 5.8 ma f hoco = 24 mhz note 5 f ih = 12 mhz note 3 normal operation v dd = 5.0 v 2.3 3.4 ma v dd = 3.0 v 2.3 3.4 ma f hoco = 12 mhz note 5 f ih = 6 mhz note 3 normal operation v dd = 5.0 v 1.6 2.2 ma v dd = 3.0 v 1.6 2.2 ma f hoco = 6 mhz note 5 f ih = 3 mhz note 3 normal operation v dd = 5.0 v 1.2 1.6 ma v dd = 3.0 v 1.2 1.6 ma hs (high-speed main) mode note 6 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.0 4.9 ma resonator connection 3.2 5.0 ma f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.0 4.9 ma resonator connection 3.2 5.0 ma f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 1.9 2.9 ma resonator connection 1.9 2.9 ma f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 1.9 2.9 ma resonator connection 1.9 2.9 ma hs (high-speed main) mode (pll operation) note 6 f pll = 48 mhz, f clk = 24 mhz note 2 normal operation v dd = 5.0 v 4.0 6.3 ma v dd = 3.0 v 4.0 6.3 ma f pll = 48 mhz, f clk = 12 mhz note 2 normal operation v dd = 5.0 v 2.6 3.9 ma v dd = 3.0 v 2.6 3.9 ma f pll = 48 mhz, f clk = 6 mhz note 2 normal operation v dd = 5.0 v 1.9 2.7 ma v dd = 3.0 v 1.9 2.7 ma subsystem clock operation f sub = 32.768 khz note 4 t a = ? 40 c normal operation resonator connection 4.1 4.9 a square wave input 4.2 5.0 a f sub = 32.768 khz note 4 t a = +25 c normal operation square wave input 4.1 4.9 a resonator connection 4.2 5.0 a f sub = 32.768 khz note 4 t a = +50 c normal operation square wave input 4.2 5.5 a resonator connection 4.3 5.6 a f sub = 32.768 khz note 4 t a = +70 c normal operation square wave input 4.2 6.3 a resonator connection 4.3 6.4 a f sub = 32.768 khz note 4 t a = +85 c normal operation square wave input 4.8 7.7 a resonator connection 4.9 7.8 a f sub = 32.768 khz note 4 t a = +105 c normal operation square wave input 6.9 19.7 a resonator connection 7.0 19.8 a ( notes and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 88 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd , or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-s peed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the rtc, 12-bit interval timer, and watchdog timer. 5. when operating frequency setting of option byte = 48 mhz. when f hoco is divided by hocodiv. when rdiv[1:0] = 00 (divided by 2: default). 6. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 24 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remarks 1. f hoco : high-speed on-chip oscillator clock frequency (max. 48 mhz) 2. f ih : main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (max. 24 mhz) 3. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 4. f pll : pll oscillation frequency 5. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 6. f clk : cpu/peripheral hardware clock frequency 7. except subsystem clock operation, temperature condition of the typ. value is t a = 25 c.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 89 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 9 f hoco = 48 mhz f ih = 24 mhz note 4 v dd = 5.0 v 0.67 2.25 ma v dd = 3.0 v 0.67 2.25 ma f hoco = 24 mhz note 7 f ih = 12 mhz note 4 v dd = 5.0 v 0.50 1.55 ma v dd = 3.0 v 0.50 1.55 ma f hoco = 12 mhz note 7 f ih = 6 mhz note 4 v dd = 5.0 v 0.41 1.21 ma v dd = 3.0 v 0.41 1.21 ma f hoco = 6 mhz note 7 f ih = 3 mhz note 4 v dd = 5.0 v 0.37 1.05 ma v dd = 3.0 v 0.37 1.05 ma hs (high-speed main) mode note 9 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.28 1.90 ma resonator connection 0.45 2.00 ma f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.28 1.90 ma resonator connection 0.45 2.00 ma f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.19 1.02 ma resonator connection 0.26 1.10 ma f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.19 1.02 ma resonator connection 0.26 1.10 ma hs (high-speed main) mode (pll operation) note 9 f pll = 48 mhz, f clk = 24 mhz note 3 v dd = 5.0 v 0.91 2.74 ma v dd = 3.0 v 0.91 2.74 ma f pll = 48 mhz, f clk = 12 mhz note 3 v dd = 5.0 v 0.85 2.31 ma v dd = 3.0 v 0.85 2.31 ma f pll = 48 mhz, f clk = 6 mhz note 3 v dd = 5.0 v 0.82 2.07 ma v dd = 3.0 v 0.82 2.07 ma subsystem clock operation f sub = 32.768 khz note 5 t a = ? 40 c square wave input 0.25 0.57 a resonator connection 0.44 0.76 a f sub = 32.768 khz note 5 t a = +25 c square wave input 0.30 0.57 a resonator connection 0.49 0.76 a f sub = 32.768 khz note 5 t a = +50 c square wave input 0.33 1.17 a resonator connection 0.63 1.36 a f sub = 32.768 khz note 5 t a = +70 c square wave input 0.46 1.97 a resonator connection 0.76 2.16 a f sub = 32.768 khz note 5 t a = +85 c square wave input 0.97 3.37 a resonator connection 1.16 3.56 a f sub = 32.768 khz note 5 t a = +105 c square wave input 3.01 15.37 a resonator connection 3.20 15.56 a i dd3 note 6 stop mode note 8 t a = ? 40 c 0.18 0.50 a t a = +25 c 0.23 0.50 a t a = +50 c 0.26 1.10 a t a = +70 c 0.29 1.90 a t a = +85 c 0.90 3.30 a t a = +105 c 2.94 15.30 a ( notes and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 90 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, usb2.0 host/function module, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip osc illator and high-speed system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rtc, 12-bit interval timer, and watchdog timer. 7. when operating frequency setting of option byte = 48 mhz. when f hoco is divided by hocodiv. when rdiv[1:0] = 00 (divided by 2: default). 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. 9. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 24 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remarks 1. f hoco : high-speed on-chip oscillator clock frequency (max. 48 mhz) 2. f ih : main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (max. 24 mhz) 3. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 4. f pll : pll oscillation frequency 5. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 6. f clk : cpu/peripheral hardware clock frequency 7. except subsystem clock operation, temperature condition of the typ. value is t a = 25 c.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 91 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit low-speed on-chip oscillator operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating current i adc notes 1, 6 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.3 1.8 ma low voltage mode, av refp = v dd = 3.0 v 0.5 0.8 ma a/d converter reference voltage current i adref note 1 75.0 a temperature sensor operating current i tmps note 1 75.0 a lvd operating current i lvd notes 1, 7 0.08 a self-programming operating current i fsp notes 1, 9 2.00 12.30 ma bgo operating current i bgo notes 1, 8 2.00 12.30 ma snooze operating current i snoz note 1 adc operation the mode is performed note 10 0.80 1.97 ma the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 1.20 3.00 ma csi operation 0.70 1.56 ma ( notes and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 92 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit usb operating current i usbh note 11 during usb communication operation under the following settings and conditions (v dd = 5.0 v, t a = +25 c): ? the internal power supply for the usb is used. ? x1 oscillation frequency (f x ) = 12 mhz, pll oscillation frequency (f pll ) = 48 mhz ? the host controller (via two ports) is set to operate in full-speed mode with four pipes (end points) used simultaneously. (pipe4: bulk out transfer (64 bytes), pipe5: bulk in transfer (64 bytes), pipe6: interrupt out transfer, pipe7: interrupt in transfer). ? the usb ports (two ports) are individually connected to a peripheral function via a 0.5 m usb cable. 9.0 ma i usbf note 11 during usb communication operation under the following settings and conditions (v dd = 5.0 v, t a = +25 c): ? the internal power supply for the usb is used. ? x1 oscillation frequency (f x ) = 12 mhz, pll oscillation frequency (f pll ) = 48 mhz ? the function controller is set to operate in full-speed mode with four pipes (end points) used simultaneously. (pipe4: bulk out transfer (64 bytes), pipe5: bulk in transfer (64 bytes), pipe6: interrupt out transfer, pipe7: interrupt in transfer). ? the usb port (one port) is connected to the host device via a 0.5 m usb cable. 2.5 ma i susp note 12 during suspended state under the following settings and conditions (v dd = 5.0 v, t a = +25 c): ? the function controller is set to full-speed mode (the udp0 pin is pulled up). ? the internal power supply for the usb is used. ? the system is set to stop mode (when the high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. when the watchdog timer is stopped.). ? the usb port (one port) is connected to the host device via a 0.5 m usb cable. 240 a ( notes and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 93 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. current flowing to v dd . 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (excluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer is in operation. 6. current flowing only to the a/d converter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 7. current flowing only to the lvd circuit. the current value of the rl78/g1c is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvd circuit operates in the operating, halt or stop mode. 8. current flowing only during data flash rewrite. 9. current flowing only during self programming. 10. for shift time to the snooze mode, see 19.3.3 snooze mode the rl78/g1c user?s manual: hardware. 11. current consumed only by the usb module and the internal power supply for the usb. 12. includes the current supplied from the pull-up resistor of the udp0 pin to the pull-down resistor of the host device, in addition to the current consumed by this mcu during the suspended state. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 94 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.4 ac characteristics 3.4.1 basic operation (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s subsystem clock (f sub ) operation 2.4 v v dd 5.5 v 28.5 30.5 31.3 s in the self programming mode hs (high-speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s external system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz f exs 32 35 khz external system clock input high-level width, low-level width t exh , t exl 2.7 v v dd 5.5 v 24 ns 2.4 v v dd < 2.7 v 30 ns t exhs , t exls 13.7 s ti00 to ti03 input high-level width, low-level width t tih , t til 1/f mck +10 ns to00 to to03 output frequency f to high-speed main mode 4.0 v v dd 5.5 v 12 mhz 2.7 v v dd < 4.0 v 8 mhz 2.4 v v dd < 2.7 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl high-speed main mode 4.0 v v dd 5.5 v 16 mhz 2.7 v v dd < 4.0 v 8 mhz 2.4 v v dd < 2.7 v 4 mhz interrupt input high-level width, low-level width t inth , t intl intp0 to intp6, intp8, intp9 2.4 v v dd 5.5 v 1 s key interrupt input low-level width t kr kr0 to kr5 2.4 v v dd 5.5 v 250 ns reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of timer mode register 0n (tmr0n). n: channel number (n = 0 to 3))
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 95 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.04167 0.0625 0.05 cycle time t cy [s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk/exclks 1/f ex / 1/f exs t exl / t exls t exh / t exhs
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 96 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 ti/to timing ti00 to ti03 t til t tih to00 to to03 1/f to interrupt request input timing intp0 to intp6, intp8, intp9 t intl t inth key interrupt input timing kr0 to kr5 t kr reset input timing reset t rsl
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 97 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.5 peripheral functions characteristics 3.5.1 serial array unit (1) during communication at same potential (uart mode) (dedicated baud rate generator output) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate f mck /12 bps theoretical value of the maximum transfer rate f mck = f clk note 2.0 mbps note the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (during communication at same potential) user's device txdq rxdq rx tx rl78 microcontroller uart mode bit width (during communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq remarks 1. q: uart number (q = 0), g: pim and pom number (g = 5) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 98 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) during communication at same potential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01), m: unit number (m = 0), n: channel number (n = 0, 1), g: pim and pom numbers (g = 0, 3, 5, 7) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01)) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd 5.5 v 250 ns 2.4 v v dd 5.5 v 500 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 ? 24 ns 2.7 v v dd 5.5 v t kcy1 /2 ? 36 ns 2.4 v v dd 5.5 v t kcy1 /2 ? 76 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 66 ns 2.7 v v dd 5.5 v 66 ns 2.4 v v dd 5.5 v 113 ns sip hold time (from sckp ) note 2 t ksi1 38 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 50 ns
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 99 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time note 5 t kcy2 4.0 v v dd 5.5 v 20 mhz < f mck 16/f mck ns f mck 20 mhz 12/f mck ns 2.7 v v dd 5.5 v 16 mhz < f mck 16/f mck ns f mck 16 mhz 12/f mck ns 2.4 v v dd 5.5 v 12/f mck and 1000 ns sckp high-/low-level width t kh2 , t kl2 4.0 v ev dd0 5.5 v t kcy2 /2 ? 14 ns 2.7 v ev dd0 5.5 v t kcy2 /2 ? 16 ns 2.4 v v dd 5.5 v t kcy2 /2 ? 36 ns sip setup time (to sckp ) note 1 t sik2 2.7 v v dd 5.5 v 1/f mck +40 ns 2.4 v v dd 5.5 v 1/f mck +60 ns sip hold time (from sckp ) note 2 t ksi2 2.7 v v dd 5.5 v 1/f mck +62 ns 2.4 v v dd 5.5 v 1/f mck +62 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v v dd 5.5 v 2/f mck +66 ns 2.4 v v dd 5.5 v 2/f mck +113 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (p img) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01), m: unit number (m = 0), n: channel number (n = 0, 1), g: pim number (g = 0, 3, 5, 7) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01))
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 100 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 csi mode connection diagram (during communication at same potential) user's device sckp sop sck si sip so rl78 microcontroller csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01) 2. m: unit number, n: channel number (mn = 00, 01)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 101 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (4) during communication at same potential (simplified i 2 c mode) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit sclr clock frequency f scl 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 100 note 1 khz hold time when sclr = ?l? t low 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 4600 ns hold time when sclr = ?h? t high 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 4600 ns data setup time (reception) t su:dat 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 1/f mck + 220 note 2 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 580 note 2 ns data hold time (transmission) t hd:dat 2.7 v v dd 5.5 v, c b = 50 pf, r b = 2.7 k 0 770 ns 2.4 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 1420 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). ( caution and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 102 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 simplified i 2 c mode mode connection diagram (during communication at same potential) user's device sdar sclr sda scl v dd r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01), g: pim number (g = 5), h: pom number (h = 3, 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0), n: channel number (n = 0, 1), mn = 00, 01)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 103 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (5) communication at different potential (2.5 v, 3 v) (uart mode) (1/2) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate reception 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f clk = 24 mhz, f mck = f clk note 2 2.0 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f clk = 24 mhz, f mck = f clk note 2 2.0 mbps 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f clk = 24 mhz, f mck = f clk note 2 2.0 mbps notes 1. use it with v dd v b . 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0), g: pim and pom number (g = 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 104 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (5) communication at different potential (2.5 v, 3 v) (uart mode) (2/2) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate transmission 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v note 1 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.6 note 2 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v note 3 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v notes 5, 6 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 7 mbps notes 1. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v maximum transfer rate = 1 [bps] { ? cb rb ln (1 ? 2.2 vb )} 3 1 transfer rate 2 ? { ? cb rb ln (1 ? 2.2 vb )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference between the transmission and reception sides. 2. this value as an example is calculated when the conditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v maximum transfer rate = 1 [bps] { ? cb rb ln (1 ? 2.0 vb )} 3 1 transfer rate 2 ? { ? cb rb ln (1 ? 2.0 vb )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference between the transmission and reception sides. 4. this value as an example is calculated when the conditions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. use it with v dd v b .
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 105 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 6. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v v dd < 3.3 v and 1.6 v v b 2.0 v maximum transfer rate = 1 [bps] { ? cb rb ln (1 ? 1.5 vb )} 3 1 transfer rate 2 ? { ? cb rb ln (1 ? 1.5 vb )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference between the transmission and reception sides. 7. this value as an example is calculated when the conditions described in the ?conditions? column are met. refer to note 6 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected uart mode connection diagram (during communication at different potential) user's device txdq rxdq rx tx v b r b rl78 microcontroller
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 106 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate remarks 1. r b [ ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0), g: pim and pom number (g = 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 107 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/2) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 600 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 1000 ns 2.4 v v dd < 3.3 v, 2.4 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 2300 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 150 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 340 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 916 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 24 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 36 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 100 ns cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. use it with v dd v b . (remarks are listed two pages after the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 108 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/2) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 162 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 354 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 958 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 38 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 38 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 200 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 390 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 966 ns sip setup time (to sckp ) note 2 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 88 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 88 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 220 ns sip hold time (from sckp ) note 2 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 38 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 38 ns delay time from sckp to sop output note 2 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 50 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 3 , c b = 30 pf, r b = 5.5 k 50 ns ( notes , cautions and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 109 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. use it with v dd v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) v b r b user's device sckp sop sck si sip so v b r b rl78 microcontroller remarks 1. r b [ ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number , n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 110 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp remarks 1. p: csi number (p = 00), m: unit number, n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 2. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 111 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (7) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time note 1 t kcy2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 20 mhz < f mck 24 mhz 24/f mck ns 8 mhz < f mck 20 mhz 20/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 12/f mck ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 20 mhz < f mck 24 mhz 32/f mck ns 16 mhz < f mck 20 mhz 28/f mck ns 8 mhz < f mck 16 mhz 24/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 12/f mck ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 20 mhz < f mck 24 mhz 72/f mck ns 16 mhz < f mck 20 mhz 64/f mck ns 8 mhz < f mck 16 mhz 52/f mck ns 4 mhz < f mck 8 mhz 32/f mck ns f mck 4 mhz 20/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 ? 24 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 ? 36 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 t kcy2 /2 ? 100 ns sip setup time (to sckp ) note 3 t sik2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 1/f mck + 40 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 1/f mck + 40 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 1/f mck + 60 ns sip hold time (from sckp ) note 4 t ksi2 1/f mck + 62 ns delay time from sckp to sop output note 5 t kso2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 240 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 428 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 2/f mck + 1146 ns notes 1. transfer rate in the snooze mode: max. 1 mbps 2. use it with v dd v b . 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( caution and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 112 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 caution select the ttl input buffer for the sip pin and sckp pin and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port i nput mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) user's device sckp sop sck si sip so v b r b rl78 microcontroller remarks 1. r b [ ]:communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number, n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 113 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp remarks 1. p: csi number (p = 00), m: unit number, n: channel number (mn = 00), g: pim and pom number (g = 0, 3, 5, 7) 2. csi01 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 114 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit sclr clock frequency f scl 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 100 note 1 khz 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 100 note 1 khz 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 100 note 1 khz hold time when sclr = ?l? t low 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1200 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 4600 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 4600 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 4650 ns hold time when sclr = ?h? t high 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 620 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 500 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 2700 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 2400 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 1830 ns ( notes , caution and remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 115 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit data setup time (reception) t su:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1/f mck + 340 note 3 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 340 note 3 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 760 note 3 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 760 note 3 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v notes 2 , c b = 100 pf, r b = 5.5 k 1/f mck + 570 note 3 ns data hold time (transmission) t hd:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 0 770 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 0 770 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 1420 ns 2.7 v v dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 100 pf, r b = 2.7 k 0 1420 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 0 1215 ns notes 1. the value must also be equal to or less than f mck /4. 2. use it with v dd v b . 3. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 116 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 simplified i 2 c mode connection diagram (during communication at different potential) user's device sdar sclr sda scl v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ]:communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00), g: pim, pom number (g = 0, 3, 5, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 117 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.5.2 serial interface iica (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit standard mode fast mode min. max. min. max. scla0 clock frequency f scl fast mode: f clk 3.5 mhz ? ? 0 400 khz standard mode: f clk 1 mhz 0 100 ? ? khz setup time of restart condition t su:sta 4.7 0.6 s hold time note 1 t hd:sta 4.0 0.6 s hold time when scla0 = ?l? t low 4.7 1.3 s hold time when scla0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s notes 1. the first clock pulse is generated after this period when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bit 1 (pior1) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of cb (communication line capacitance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k fast mode: c b = 320 pf, r b = 1.1 k iica serial transfer timing t low t buf t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scla0 sdaa0
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 118 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.5.3 usb (1) electrical specifications (t a = ? 40 to +105 c, 3.0 v uv dd 3.6 v, 3.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit uv dd uv dd input voltage characteristic uv dd v dd = 3.0 to 5.5 v, pxxcon = 1, vdduseb = 0 (uv dd v dd ) 3.0 3.3 3.6 v uv dd output voltage characteristic uv dd v dd = 4.0 to 5.5 v, pxxcon = vdduseb = 1 3.0 3.3 3.6 v uv bus uv bus input voltage characteristic uv bus function 4.35 (4.02 note ) 5.00 5.25 v host 4.75 5.00 5.25 v note value of instantaneous voltage (t a = ? 40 to +105 c, 3.0 v uv dd 3.6 v, 3.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit udpi/udmi pins input characteristic (fs/ls receiver) input voltage v ih 2.0 v v il 0.8 v difference input sensitivity v di | udp voltage ? udm voltage | 0.2 v difference common mode range v cm 0.8 2.5 v udpi/udmi pins output characteristic (fs driver) output voltage v oh i oh = ? 200 a 2.8 3.6 v v ol i ol = 2.4 ma 0 0.3 v transi-ti on time rising t fr rising: from 10% to 90 % of amplitude, falling: from 90% to 10 % of amplitude, cl = 50 pf 4 20 ns falling t ff 4 20 ns matching (tfr/tff) v frfm 90 111.1 % crossover voltage v fcrs 1.3 2.0 v output impedance z drv uv dd voltage = 3.3 v, pin voltage = 1.65 v 28 44 udpi/udmi pins output characteristic (ls driver) output voltage v oh 2.8 3.6 v v ol 0 0.3 v transi-ti on time rising t lr rising: from 10% to 90 % of amplitude, falling: from 90% to 10 % of amplitude, cl = 200 to 600 pf when the host controller function is selected: the udmi pin (i = 0, 1) is pulled up via 1.5 k . when the function controller function is selected: the udp0 and udm0 pins are individually pulled down via 15 k 75 300 ns falling t lf 75 300 ns matching (tfr/tff) note v ltfm 80 125 % crossover voltage note v lcrs 1.3 2.0 v udpi/udmi pins pull-up, pull-down pull-down resistor r pd 14.25 24.80 k pull-up resistor (i = 0 only) idle r pui 0.9 1.575 k recep-t ion r pua 1.425 3.09 k uv bus uv bus pull-down resistor r vbus uv bus voltage = 5.5 v 1000 k uv bus input voltage v ih 3.20 v v il 0.8 v note excludes the first signal transition from the idle state. remark i = 0, 1
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 119 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 timing of udpi and udmi udpi udmi 90 % 90 % 10 % 10 % v crs (crossover voltage) t r t f (2) bc standard (t a = ? 40 to +105 c, 3.0 v uv dd 3.6 v, 3.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit usb standard bc1.2 udpi sink current i dp_sink 25 175 a udmi sink current i dm_sink 25 175 a dcd source current i dp_src 7 13 a dedicated charging port resistor r dcp_dat 0 v < udp/udm voltage < 1.0 v 200 data detection voltage v dat_ref 0.25 0.4 v udpi source voltage v dp_src output current 250 a 0.5 0.7 v udmi source voltage v dm_src output current 250 a 0.5 0.7 v remark i = 0, 1
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 120 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) bc option standard (host) (t a = ? 40 to +105 c, 4.75 v uv bus 5.25 v, 3.0 v uv dd 3.6 v, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit udpi output voltage (uv bus divider ratio) ? vdouei = 1 vdseli [3:0] (i = 0, 1) 1000 v p20 38 40 42 % uv bus 1001 v p27 51.6 53.6 55.6 % uv bus 1010 v p20 38 40 42 % uv bus 1100 v p33 60 66 72 % uv bus udmi output voltage (uv bus divider ratio) ? vdouei = 1 vdseli [3:0] (i = 0, 1) 1000 v m20 38 40 42 % uv bus 1001 v m20 38 40 42 % uv bus 1010 v m27 51.6 53.6 55.6 % uv bus 1100 v m33 60 66 72 % uv bus udpi comparing voltage note 1 (uv bus divider ratio) ? vdouei = 1 ? cusdetei = 1 vdseli [3:0] (i = 0, 1) 1000 v hdetp_up0 the rise of pin voltage detection voltage 56.2 % uv bus v hdetp_dwn0 the fall of pin voltage detection voltage 29.4 % uv bus 1001 v hdetp_up1 the rise of pin voltage detection voltage 60.5 % uv bus v hdetp_dwn1 the fall of pin voltage detection voltage 45.0 % uv bus 1010 v hdetp_up2 the rise of pin voltage detection voltage 56.2 % uv bus v hdetp_dwn2 the fall of pin voltage detection voltage 29.4 % uv bus udmi comparing voltage note 1 (uv bus divider ratio) ? vdouei = 1 ? cusdetei = 1 vdseli [3:0] (i = 0, 1) 1000 v hdetm_up0 the rise of pin voltage detection voltage 56.2 % uv bus v hdetm_dwn0 the fall of pin voltage detection voltage 29.4 % uv bus 1001 v hdetm_up1 the rise of pin voltage detection voltage 56.2 % uv bus v hdetm_dwn1 the fall of pin voltage detection voltage 29.4 % uv bus 1010 v hdetm_up2 the rise of pin voltage detection voltage 60.5 % uv bus v hdetm_dwn2 the fall of pin voltage detection voltage 45.0 % uv bus udpi pull-up detection note 2 connect detection with the full speed function (pull-up resistor) 1000 r hdet_pull in full-speed mode, the power supply voltage range of pull-up resistors connected to the usb function module is between 3.0 v and 3.6 v. 1.575 k 1001 1010 udmi pull-up detection note 2 connect detection with the low-speed (pull-up resistor) 1000 r hdet_pull in low-speed mode, the power supply voltage range of pull-up resistors connected to the usb function module is between 3.0 v and 3.6 v. 1.575 k 1001 1010 udmi sink current detection note 2 connect detection with the bc1.2 portable device (sink resistor) 1000 i hdet_sink 25 a 1001 1010 notes 1. if the voltage output from udpi or udmi (i = 0, 1) exceeds the range of the max and min values prescribed in this specification, dpcusdeti (bit 8) and dmcusdeti (bit 9) of the usbbcopti register are set to 1. 2. if the pull-up resistance or sink current prescribed in this specification is applied to udpi or udmi (i = 0, 1), dpcusdeti (bit 8) and dmcusdeti (bit 9) of the usbbcopti register are set to 1. remark i = 0, 1
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 121 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (4) bc option standard (function) (t a = ? 40 to +105 c, 4.35 v uv bus 5.25 v, 3.0 v uv dd 3.6 v, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit udpi/udmi input reference voltage (uv bus divider ratio) ? vdouei = 0 (i = 0)) vdseli [3:0] (i = 0) 0000 v ddet0 27 32 37 % uv bus 0001 v ddet1 29 34 39 % uv bus 0010 v ddet2 32 37 42 % uv bus 0011 v ddet3 35 40 45 % uv bus 0100 v ddet4 38 43 48 % uv bus 0101 v ddet5 41 46 51 % uv bus 0110 v ddet6 44 49 54 % uv bus 0111 v ddet7 47 52 57 % uv bus 1000 v ddet8 51 56 61 % uv bus 1001 v ddet9 55 60 65 % uv bus 1010 v ddet10 59 64 69 % uv bus 1011 v ddet11 63 68 73 % uv bus 1100 v ddet12 67 72 77 % uv bus 1101 v ddet13 71 76 81 % uv bus 1110 v ddet14 75 80 85 % uv bus 1111 v ddet15 79 84 89 % uv bus
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 122 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.6 analog characteristics 3.6.1 a/d converter characteristics classification of a/d converter characteristics input channel reference voltage reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani7 refer to 3.6.1 (1) . refer to 3.6.1 (3) . refer to 3.6.1 (4) . ani16, ani17, ani19 refer to 3.6.1 (2) . internal reference voltage temperature sensor output voltage refer to 3.6.1 (1) . ? (1) when av ref (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani2 to ani7, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 1.2 3.5 lsb conversion time t conv 10-bit resolution target pin: ani2 to ani7 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 0.25 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 1.5 lsb analog input voltage v ain ani2 to ani7 0 av refp v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 4 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v ( notes are listed on the next page.)
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 123 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . 4. refer to 3.6.2 temperature sensor/internal reference voltage characteristics .
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 124 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani16, ani17, ani19 (t a = ? 40 to +105 c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 1.2 5.0 lsb conversion time t conv 10-bit resolution target ani pin: ani16, ani17, ani19 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 0.35 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 0.35 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 3.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 2.0 lsb analog input voltage v ain ani16, ani17, ani19 0 av refp and v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd .
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 125 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (3) reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target ani pin: ani0 to ani7, ani16, ani17, ani19, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error notes 1, 2 ainl 10-bit resolution 2.4 v v dd 5.5 v 1.2 7.0 lsb conversion time t conv 10-bit resolution target ani pin: ani0 to ani7, ani16, ani17, ani19 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target ani pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr full-scale error notes 1, 2 efs 10-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr integral linearity error note 1 ile 10-bit resolution 2.4 v v dd 5.5 v 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.4 v v dd 5.5 v 2.0 lsb analog input voltage v ain ani0 to ani7, ani16, ani17, ani19 0 v dd v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 3 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature sensor/internal reference voltage characteristics .
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 126 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 (4) when reference voltage (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani0 to ani7, ani16, ani17, ani19 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm note 4 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 8-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.4 v v dd 5.5 v 2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.4 v v dd 5.5 v 1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature sensor/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage ( ? ) = av refm .
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 127 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode ) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/ c operation stabilization wait time t amp 5 s 3.6.3 por circuit characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.45 1.51 1.57 v v pdr power supply fall time 1.44 1.50 1.56 v minimum pulse width note t pw 300 s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock (f main ) is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). t p w v por v pdr or 0.7 v su pply voltage (v dd )
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 128 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +105 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage supply voltage level v lvd0 power supply rise time 3.90 4.06 4.22 v power supply fall time 3.83 3.98 4.13 v v lvd1 power supply rise time 3.60 3.75 3.90 v power supply fall time 3.53 3.67 3.81 v v lvd2 power supply rise time 3.01 3.13 3.25 v power supply fall time 2.94 3.06 3.18 v v lvd3 power supply rise time 2.90 3.02 3.14 v power supply fall time 2.85 2.96 3.07 v v lvd4 power supply rise time 2.81 2.92 3.03 v power supply fall time 2.75 2.86 2.97 v v lvd5 power supply rise time 2.70 2.81 2.92 v power supply fall time 2.64 2.75 2.86 v v lvd6 power supply rise time 2.61 2.71 2.81 v power supply fall time 2.55 2.65 2.75 v v lvd7 power supply rise time 2.51 2.61 2.71 v power supply fall time 2.45 2.55 2.65 v minimum pulse width t lw 300 s detection delay time t ld 300 s
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 129 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +105 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvdd0 vpoc2, vpoc1, vpoc0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 v v lvdd1 lvis1, lvis0 = 1, 0 rising release reset voltage 2.81 2.92 3.03 v falling interrupt voltage 2.75 2.86 2.97 v v lvdd2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.90 3.02 3.14 v falling interrupt voltage 2.85 2.96 3.07 v v lvdd3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.90 4.06 4.22 v falling interrupt voltage 3.83 3.98 4.13 v 3.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 3.4 ac characteristics.
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 130 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the por detection voltage. when the voltage drops, the data is retained before a por reset is effected, but data is not retained when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 3.8 flash memory programming characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.4 v v dd 5.5 v 1 24 mhz number of code flash rewrites c erwr retaining years: 20 years t a = +85 c 1,000 times number of data flash rewrites notes 1, 2, 3 retaining years: 1 year t a = +25 c 1,000,000 retaining years: 5 years t a = +85 c 100,000 retaining years: 20 years t a = +85 c 10,000 notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renes as electronics self programming library. 3. these specifications show the characteristics of the flash memory and the results obtained from renesas electronics reliability testing. 3.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps
rl78/g1c 3. electrical specifications (g: t a = -40 to +105 c) page 131 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 3.10 timing specs for switching flash memory programming modes (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit 723 s + t hd processing time t su <4> 00h reception (toolrxd, tooltxd mode) <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until an external reset ends t hd : how long to keep the tool0 pin at the low level from when the external and internal resets end (excluding the processing time of the firmware to control the flash memory)
rl78/g1c 4. package drawings page 132 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 4. package drawings 4.1 32-pin products r5f10jbcafp, r5f10kbcafp r5f10jbcgfp, r5f10kbcgfp 0.145 0.055 (unit:mm) item dimensions d e hd he a a1 a2 7.00 0.10 7.00 0.10 9.00 0.20 9.00 0.20 1.70 max. 0.10 0.10 1.40 c e x y 0.80 0.20 0.10 l 0.50 0.20 0 to 8 0.37 0.05 b note 1.dimensions ? 1? and ? 2? do not include mold flash. 2.dimension ? 3? does not include trim offset. y e xb m l c hd he a1 a2 a d e detail of lead end 8 16 1 32 9 17 25 24 2 1 3 jeita package code renesas code previous code mass (typ.) [g] p-lqfp32-7x7-0.80 plqp0032gb-a p32ga-80-gbt-1 0.2
rl78/g1c 4. package drawings page 133 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 r5f10jbcana, r5f10kbcana r5f10jbcgna, r5f10kbcgna 2012 renesas electronics corporation. all rights reserved. s y e lp sx ba b m a d e 24 16 17 8 9 1 32 a s b a d e a b e lp x y 5.00 0.05 0.50 0.05 0.05 5.00 0.05 0.75 0.05 0.25 0.05 + 0.07 0.40 0.10 s d2 e2 (unit:mm) item dimensions 25 detail of a part ? exposed die pad item d2 e2 a min nom max 3.45 3.50 exposed die pad variations 3.55 min nom max 3.45 3.50 3.55 jeita package code renesas code previous code mass (typ.) [g] p-hwqfn32-5x5-0.50 pwqn0032kb-a p32k8-50-3b4-3 0.06
rl78/g1c 4. package drawings page 134 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 4.2 48-pin products r5f10jgcafb, r5f10kgcafb r5f10jgcgfb, r5f10kgcgfb jeita package code renesas code pre v ious code mass (typ.) [g] p-lfqfp48-7x7-0.50 plqp0048kf-a p48ga-50-8eu-1 0.16 s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 12 24 1 48 13 25 37 36 2012 renesas electronics corporation. all rights reserved.
rl78/g1c 4. package drawings page 135 of 135 r01ds0348ej0110 rev.1.10 nov 15, 2013 r5f10jgcana, r5f10kgcana r5f10jgcgna, r5f10kgcgna 2012 renesas electronics corporation. all rights reserved. detail of a part s y e lp sx ba b m a d e 36 37 24 25 12 13 1 48 a s b a item dimensions d e a b e lp x y 7.00 0.05 0.50 0.05 0.05 7.00 0.05 0.75 0.05 0.25 0.05 + 0.07 0.40 0.10 (unit:mm ) s d2 e2 ? exposed die pad item d2 e2 a min nom max 5.45 5.50 exposed die pad variations 5.55 min nom max 5.45 5.50 5.55 jeita package code renesas code previous code mass (typ.) [g] p-hwqfn48-7x7-0.50 pwqn0048kb-a p48k8-50-5b4-4 0.13
all trademarks and registered trademarks are the property of their respective owners. c - 1 revision history rl78/g1c data sheet rev. date description page summary 0.01 sep 20, 2012 - first edition issued 1.00 aug 08, 2013 throughout deletion of the bar over sck and sckxx renaming of f ext to f exs renaming of interval timer (unit) to 12-bit interval timer addition of products for g: industrial applications (t a = -40 to +105 c ) 1 change of 1.1 features 2 change of 1.2 list of part numbers 3 modification of figure 1-1. part number, memory size, and package of rl78/g1c 4, 5 addition of remark to 1.3 pin configuration (top view) 15, 16 change of 1.6 outline of functions 17 to 76 addition of a whole chapter 77 to 131 addition of a whole chapter 132 addition of products for g: industrial applications (t a = -40 to +105 c ) 1.10 nov 15, 2013 77 caution 3 added. 79 note for operating ambient temperature in 3.1 absolute maximum ratings deleted. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc.
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device.
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